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Add minimal target for Arty Board platform #592

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Add minimal target for Arty Board platform #592

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rw1nkler
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@rw1nkler rw1nkler commented Dec 7, 2020

This commit adds a simple minimal target for the Arty board. The target is used to demonstrate the SymbiFlow toolchain usage with the litex-buildenv project. Custom target is needed since the default BaseSoC class uses DNA, which is not supported by SymbiFlow.

Additionally, this PR changes the Arty Board part name. The same chip version is used in the main LiteX repository:
https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/arty.py#L317

The detailed description about SymbiFlow usage prepared for the Wiki is available [HERE]

mithro
mithro approved these changes Dec 8, 2020
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LGTM, but I guess we need to move to GitHub actions for this repo.

whatnick pushed a commit to whatnick/litex-buildenv that referenced this pull request Jan 3, 2021
@mateusz-holenko
Updating submodules.
ecfc133 
 * litedram changed from edd5e0e to f51052f
    * f51052f - core/controller: fix burst_length regression introduced by timvideos#206. <Florent Kermarrec>
    * c4ac887 - Merge pull request timvideos#206 from antmicro/jboc/gensdrphy <enjoy-digital>
    * 2c5fc66 - phy/gensdrphy: fix problems with half-rate phy, tested on minispartan6 <Jędrzej Boczar>
    * 7f55e2e - phy/gensdrphy: add half-rate PHY <Jędrzej Boczar>

 * liteeth changed from dbe15f1 to 792013a
    * 792013a - mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in timvideos#43). <Florent Kermarrec>
    * 1d76d02 - frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream). <Florent Kermarrec>

 * litepcie changed from 5668679 to 0b6a4bb
    * 0b6a4bb - software/kernel/main: enable up to 8 dma channels. <Florent Kermarrec>
    * f106f74 - software/user/litepcie_util: reset dma_test errors to 0 on each loop. <Florent Kermarrec>
    * 4d506fb - litepcie_gen: remove CSR software reset (no longer handled by software. <Florent Kermarrec>
    * f258b88 - phy/ultrascale: fix padding on s_axis_cc_header0 (requesterid was shifted by 1-bit). <Florent Kermarrec>
    * ccdd7a2 - core/msi/LitePCIeMSIX: avoid reserved registers when width > 32. <Florent Kermarrec>

 * litex changed from e7646416 to 9fc488bd
    *   9fc488bd - Merge pull request timvideos#597 from antmicro/jboc/litex-buildenv-add-adapter-fix <enjoy-digital>
    |\
    | * 07bc589c - fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed <Jędrzej Boczar>
    * |   b9251950 - Merge pull request timvideos#595 from betrusted-io/master <enjoy-digital>
    |\ \
    | * | 53a567da - wire up missing register bits. <bunnie>
    * | |   87d7f6e7 - Merge pull request timvideos#598 from sergachev/master <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | 8656ea9b - interconnect/csr_bus: fix paged access warning <Ilia Sergachev>
    |/ /
    * | 4a18b828 - software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. <Florent Kermarrec>
    * | 100aa5a4 - soc/cores/spi/SPIMaster: rewrite/simplify. - Make sure MOSI is latched on start, MISO is stable during Xfer (last value). - Allow clk_divider down to 2. - improve test errors reporting with hex() on AssertEqual. <Florent Kermarrec>
    |/
    * 63c19ff4 - liblitesdcard/spisdcard: update comments. <Florent Kermarrec>
    * 1f34f6ef - soc/cores/spi: make sure done and miso are synchronous. <Florent Kermarrec>
    * 754f140a - spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. <Florent Kermarrec>
    * 8143f1a0 - soc/cores/spi: make sure miso is stable during xfer. <Florent Kermarrec>
    * ac35e158 - bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. <Florent Kermarrec>
    *   ee4b1d81 - Merge pull request timvideos#594 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * 229da572 - soc/interconnect/axi: propagate response errors in AXILiteDownConverter <Jędrzej Boczar>
    | * 93bcc94b - soc/interconnect/axi: implement AXILite down-converter <Jędrzej Boczar>
    * | 21c48eed - Merge pull request timvideos#593 from antmicro/jboc/axi-lite <enjoy-digital>
    |\|
    | * 0be607da - soc/integration: revert `bus` argument for add_ram/add_rom <Jędrzej Boczar>
    | * 2700ec3c - soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() <Jędrzej Boczar>
    | * f3072d49 - soc/interconnect/axi: add connect methods for convenience <Jędrzej Boczar>
    | * 78a631f3 - test/axi: add AXILite2CSR and AXILiteSRAM tests <Jędrzej Boczar>
    | * a5be2cd2 - soc/interconnect/axi: improve SRAM/CSR access speed <Jędrzej Boczar>
    | * d8a242d8 - soc/interconnect: add AXILite SRAM <Jędrzej Boczar>
    | * b692b2a3 - soc/interconnect: add AXILite2CSR bridge <Jędrzej Boczar>
    | * 35149c4e - soc/integration: update add_adapter to convert between AXILite/Wishbone <Jędrzej Boczar>
    * |   e12bebb8 - Merge pull request timvideos#592 from antmicro/fix-symbiflow-makefile <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 3f7568de - symbiflow: changed toolchain command names in Makefile <Alessandro Comodi>
    |/
    * 6671eb62 - build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. <Florent Kermarrec>
    * ae3c78f6 - build/lattice/trellis: fix spimode typo. <Florent Kermarrec>
    * 7c381dad - Merge pull request timvideos#588 from oskirby/trellis-spimode <enjoy-digital>
    * 0aec5b0f - trellis: Add option to select SPI mode. <Owen Kirby>

 * litex-boards changed from 1f98bc5 to 2ce24df
    * 2ce24df - platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3). <Florent Kermarrec>
    * 135c387 - platforms/ulx3s: add assertion for supported devices. <Florent Kermarrec>
    * 851378f - platforms/trellisboard: move ddram_vtt_en. <Florent Kermarrec>
    *   165f9ea - Merge pull request timvideos#91 from antmicro/jboc/gensdrphy <enjoy-digital>
    |\
    | * 02f53e6 - targets/minispartan6: add support for HalfRateGENSDRPHY <Jędrzej Boczar>
    * 82f4553 - Merge pull request timvideos#90 from jersey99/master <enjoy-digital>
    * 44ad902 - platforms/kc705.py: LPC DP0_M2C/C2M diff pair <Vamsi K Vytla>

 * migen changed from 0.6.dev-351-gfa7bed2 to 0.6.dev-354-g7bc4eb1
    * 7bc4eb1 - xilinx: add DDRInput for Spartan6 (timvideos#214) <Thomas Spurden>
    * 731c192 - metlino: add SFP CTL pins <Harry Ho>
    * 12e7ba6 - Fix Si5324 reset. <Paweł Kulik>

Full submodule status
--
 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06)
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 f51052f8b737156d1e257eff7cd3259cb56d0d1b litedram (2020.04-69-gf51052f)
 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a)
 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04)
 0b6a4bb6e742fd4de38d7ca3674f91acc5985b35 litepcie (2020.04-56-g0b6a4bb)
 b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3)
 15179cb46f68bff1679631a8bade6f7e1607a40a litescope (2020.04-2-g15179cb)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 9fc488bdf670c69193a6fa14e5f0c218db8b0ffe litex (2020.04-492-g9fc488bd)
 2ce24df76dda20cff9ac40c334300d5dc1311d60 litex-boards (2020.04-132-g2ce24df)
 f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD)
 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1)
 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253)
 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380)
 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master)
 af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117)
 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489)
 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b)
 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)
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nickoe commented Feb 4, 2021

@rw1nkler Is the "updaging submodules" commit intentional? It does not seem like this is needed to accomplish the original description of this PR.

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