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PoC: create a syscall by forcing the next CPU instruction #259

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PoC: create a syscall by forcing the next CPU instruction #259

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e8762d8
(fpga) First attempt at PoC of HW trampoline for syscall.
secworks Aug 29, 2024
fe83504
(fpga) Possibly working syscall hw functionality.
secworks Aug 29, 2024
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36 changes: 36 additions & 0 deletions hw/application_fpga/core/tk1/rtl/tk1.v
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,9 @@ module tk1(
output wire force_trap,
output system_reset,

output wire [31 : 0] syscall_instr,
output wire syscall,

output wire [14 : 0] ram_addr_rand,
output wire [31 : 0] ram_data_rand,

Expand Down Expand Up @@ -81,6 +84,9 @@ module tk1(

localparam ADDR_BLAKE2S = 8'h10;

localparam ADDR_SYSCALL_INSTR = 8'h12;
localparam ADDR_SYSCALL_START = 8'h13;

localparam ADDR_CDI_FIRST = 8'h20;
localparam ADDR_CDI_LAST = 8'h27;

Expand Down Expand Up @@ -138,6 +144,12 @@ module tk1(
reg [31 : 0] blake2s_addr_reg;
reg blake2s_addr_we;

reg [31 : 0] syscall_instr_reg;
reg syscall_instr_we;

reg syscall_reg;
reg syscall_new;

reg [23 : 0] cpu_trap_ctr_reg;
reg [23 : 0] cpu_trap_ctr_new;
reg [2 : 0] cpu_trap_led_reg;
Expand Down Expand Up @@ -175,6 +187,8 @@ module tk1(

wire [31:0] udi_rdata;

reg start_syscall;

`ifdef INCLUDE_SPI_MASTER
reg spi_enable;
reg spi_enable_vld;
Expand Down Expand Up @@ -204,6 +218,9 @@ module tk1(

assign system_reset = system_reset_reg;

assign syscall_instr = syscall_instr_reg;
assign syscall = syscall_reg;


//----------------------------------------------------------------
// Module instance.
Expand Down Expand Up @@ -268,6 +285,8 @@ module tk1(
app_start_reg <= 32'h0;
app_size_reg <= 32'h0;
blake2s_addr_reg <= 32'h0;
syscall_instr_reg <= 32'h0;
syscall_reg <= 1'h0;
cdi_mem[0] <= 32'h0;
cdi_mem[1] <= 32'h0;
cdi_mem[2] <= 32'h0;
Expand All @@ -291,6 +310,7 @@ module tk1(
cpu_trap_ctr_reg <= cpu_trap_ctr_new;

system_reset_reg <= system_reset_new;
syscall_reg <= syscall_new;

gpio1_reg[0] <= gpio1;
gpio1_reg[1] <= gpio1_reg[0];
Expand Down Expand Up @@ -326,6 +346,10 @@ module tk1(
blake2s_addr_reg <= write_data;
end

if (syscall_instr_we) begin
syscall_instr_reg <= write_data;
end

if (cdi_mem_we) begin
cdi_mem[address[2 : 0]] <= write_data;
end
Expand Down Expand Up @@ -436,6 +460,8 @@ module tk1(
app_start_we = 1'h0;
app_size_we = 1'h0;
blake2s_addr_we = 1'h0;
syscall_instr_we = 1'h0;
syscall_new = 1'h0;
cdi_mem_we = 1'h0;
cdi_mem_we = 1'h0;
ram_addr_rand_we = 1'h0;
Expand Down Expand Up @@ -495,6 +521,16 @@ module tk1(
end
end

if (address == ADDR_SYSCALL_INSTR) begin
if (!switch_app_reg) begin
syscall_instr_we = 1'h1;
end
end

if (address == ADDR_SYSCALL_START) begin
syscall_new = 1'h1;
end

if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (!switch_app_reg) begin
cdi_mem_we = 1'h1;
Expand Down
11 changes: 11 additions & 0 deletions hw/application_fpga/rtl/application_fpga.v
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Original file line number Diff line number Diff line change
Expand Up @@ -149,6 +149,8 @@ module application_fpga(
wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand;
wire tk1_system_reset;
wire [31 : 0] tk1_syscall_instr;
wire tk1_syscall;
/* verilator lint_on UNOPTFLAT */


Expand Down Expand Up @@ -328,6 +330,9 @@ module application_fpga(

.system_reset(tk1_system_reset),

.syscall_instr(tk1_syscall_instr),
.syscall(tk1_syscall),

.ram_addr_rand(ram_addr_rand),
.ram_data_rand(ram_data_rand),

Expand Down Expand Up @@ -434,6 +439,12 @@ module application_fpga(
muxed_rdata_new = ILLEGAL_INSTRUCTION;
muxed_ready_new = 1'h1;
end

else if (tk1_syscall) begin
muxed_rdata_new = tk1_syscall_instr;
muxed_ready_new = 1'h1;
end

else begin
case (area_prefix)
ROM_PREFIX: begin
Expand Down
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