Update Verilog version to 2005 for linting

Signed-off-by: Joachim Strömbergson <[email protected]>
tillitis · Apr 24, 2024 · e961f46 · e961f46
1 parent f655196
commit e961f46
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Showing 6 changed files with 7 additions and 7 deletions.
diff --git a/hw/application_fpga/core/timer/toolruns/Makefile b/hw/application_fpga/core/timer/toolruns/Makefile
@@ -21,7 +21,7 @@ CC = iverilog
 CC_FLAGS = -Wall
 
 LINT = verilator
-LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+LINT_FLAGS = +1364-2005ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
 
 all: top.sim core.sim
@@ -67,7 +67,7 @@ help:
 	@echo "sim-top:      Run top level simulation."
 	@echo "sim-core:     Run core level simulation."
 	@echo "lint-core:    Lint core rtl source files."
-	@echo "lint-core:    Lint top rtl source files."
+	@echo "lint-top:     Lint top rtl source files."
 	@echo "clean:        Delete all built files."
 
 #===================================================================

diff --git a/hw/application_fpga/core/tk1/toolruns/Makefile b/hw/application_fpga/core/tk1/toolruns/Makefile
@@ -18,7 +18,7 @@ CC = iverilog
 CC_FLAGS = -Wall
 
 LINT = verilator
-LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+LINT_FLAGS = +1364-2005ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
 
 all: top.sim

diff --git a/hw/application_fpga/core/touch_sense/toolruns/Makefile b/hw/application_fpga/core/touch_sense/toolruns/Makefile
@@ -18,7 +18,7 @@ CC = iverilog
 CC_FLAGS = -Wall
 
 LINT = verilator
-LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+LINT_FLAGS = +1364-2005ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
 
 all: top.sim

diff --git a/hw/application_fpga/core/trng/toolruns/Makefile b/hw/application_fpga/core/trng/toolruns/Makefile
@@ -18,7 +18,7 @@ CC = iverilog
 CC_FLAGS = -Wall
 
 LINT = verilator
-LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+LINT_FLAGS = +1364-2005ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
 
 all: top.sim

diff --git a/hw/application_fpga/core/uart/toolruns/Makefile b/hw/application_fpga/core/uart/toolruns/Makefile
@@ -18,7 +18,7 @@ CC = iverilog
 CC_FLAGS = -Wall
 
 LINT = verilator
-LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+LINT_FLAGS = +1364-2005ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
 
 all: top.sim

diff --git a/hw/application_fpga/core/uds/toolruns/Makefile b/hw/application_fpga/core/uds/toolruns/Makefile
@@ -18,7 +18,7 @@ CC = iverilog
 CC_FLAGS = -Wall
 
 LINT = verilator
-LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+LINT_FLAGS = +1364-2005ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
 
 all: top.sim