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Update SpinalHDL_Chinese_Doc.md
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JiangyuanGu authored Oct 31, 2022
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4 changes: 2 additions & 2 deletions merge all/SpinalHDL_Chinese_Doc.md
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Expand Up @@ -2778,8 +2778,8 @@ Verilog
| x >> y | 逻辑右移, y: UInt | Bits(w(x) bits) |
| x << y | 逻辑左移, y: Int | Bits(w(x)+y bits) |
| x << y | 逻辑左移, y: UInt | Bits(w(x)+max(y) bits) |
| x|>> | >> y | 逻辑右移, y: Int/UInt | Bits(w(x) bits) |
| x|<< | << y | 逻辑左移, y: Int/UInt | Bits(w(x) bits) |
| x\|>>y | >> y | 逻辑右移, y: Int/UInt | Bits(w(x) bits) |
| x\|<<y | << y | 逻辑左移, y: Int/UInt | Bits(w(x) bits) |
| x.rotateLeft(y) | 逻辑循环左移, y: UInt/Int | Bits(w(x) bits) |
| x.rotateRight(y) | 逻辑循环右移, y: UInt/Int | Bits(w(x) bits) |
| x.clearAll[()] | 清除所有bits | |
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