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Move entirely to array-based SIMD #1624

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Aug 8, 2024
Merged

Move entirely to array-based SIMD #1624

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264b1ff
Move entirely to array-based SIMD
scottmcm Aug 7, 2024
fed7b5d
Keep `Debug` the same
scottmcm Aug 7, 2024
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24 changes: 12 additions & 12 deletions crates/core_arch/src/aarch64/neon/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,12 +21,12 @@ use crate::{
use stdarch_test::assert_instr;

types! {
#![stable(feature = "neon_intrinsics", since = "1.59.0")]

/// ARM-specific 64-bit wide vector of one packed `f64`.
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub struct float64x1_t(f64); // FIXME: check this!
pub struct float64x1_t(1 x f64); // FIXME: check this!
/// ARM-specific 128-bit wide vector of two packed `f64`.
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub struct float64x2_t(f64, f64);
pub struct float64x2_t(2 x f64);
}

/// ARM-specific type containing two `float64x1_t` vectors.
Expand Down Expand Up @@ -1061,7 +1061,7 @@ pub unsafe fn vabsq_s64(a: int64x2_t) -> int64x2_t {
#[cfg_attr(test, assert_instr(bsl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vbsl_f64(a: uint64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
let not = int64x1_t(-1);
let not = int64x1_t::splat(-1);
transmute(simd_or(
simd_and(a, transmute(b)),
simd_and(simd_xor(a, transmute(not)), transmute(c)),
Expand All @@ -1073,7 +1073,7 @@ pub unsafe fn vbsl_f64(a: uint64x1_t, b: float64x1_t, c: float64x1_t) -> float64
#[cfg_attr(test, assert_instr(bsl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vbsl_p64(a: poly64x1_t, b: poly64x1_t, c: poly64x1_t) -> poly64x1_t {
let not = int64x1_t(-1);
let not = int64x1_t::splat(-1);
simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c))
}
/// Bitwise Select. (128-bit)
Expand All @@ -1082,7 +1082,7 @@ pub unsafe fn vbsl_p64(a: poly64x1_t, b: poly64x1_t, c: poly64x1_t) -> poly64x1_
#[cfg_attr(test, assert_instr(bsl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vbslq_f64(a: uint64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
let not = int64x2_t(-1, -1);
let not = int64x2_t::splat(-1);
transmute(simd_or(
simd_and(a, transmute(b)),
simd_and(simd_xor(a, transmute(not)), transmute(c)),
Expand All @@ -1094,7 +1094,7 @@ pub unsafe fn vbslq_f64(a: uint64x2_t, b: float64x2_t, c: float64x2_t) -> float6
#[cfg_attr(test, assert_instr(bsl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vbslq_p64(a: poly64x2_t, b: poly64x2_t, c: poly64x2_t) -> poly64x2_t {
let not = int64x2_t(-1, -1);
let not = int64x2_t::splat(-1);
simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c))
}

Expand Down Expand Up @@ -1976,7 +1976,7 @@ pub unsafe fn vdup_n_p64(value: p64) -> poly64x1_t {
#[cfg_attr(test, assert_instr(nop))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vdup_n_f64(value: f64) -> float64x1_t {
float64x1_t(value)
float64x1_t::splat(value)
}

/// Duplicate vector element to vector or scalar
Expand All @@ -1994,7 +1994,7 @@ pub unsafe fn vdupq_n_p64(value: p64) -> poly64x2_t {
#[cfg_attr(test, assert_instr(dup))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vdupq_n_f64(value: f64) -> float64x2_t {
float64x2_t(value, value)
float64x2_t::splat(value)
}

/// Duplicate vector element to vector or scalar
Expand Down Expand Up @@ -2040,7 +2040,7 @@ pub unsafe fn vmovq_n_f64(value: f64) -> float64x2_t {
#[cfg_attr(all(test, target_env = "msvc"), assert_instr(dup))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vget_high_f64(a: float64x2_t) -> float64x1_t {
float64x1_t(simd_extract!(a, 1))
float64x1_t([simd_extract!(a, 1)])
}

/// Duplicate vector element to vector or scalar
Expand All @@ -2058,7 +2058,7 @@ pub unsafe fn vget_high_p64(a: poly64x2_t) -> poly64x1_t {
#[cfg_attr(test, assert_instr(nop))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn vget_low_f64(a: float64x2_t) -> float64x1_t {
float64x1_t(simd_extract!(a, 0))
float64x1_t([simd_extract!(a, 0)])
}

/// Duplicate vector element to vector or scalar
Expand Down
9 changes: 5 additions & 4 deletions crates/core_arch/src/arm/dsp.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -23,15 +23,16 @@
#[cfg(test)]
use stdarch_test::assert_instr;

use crate::intrinsics::simd::simd_shuffle;
use crate::mem::transmute;

types! {
#![unstable(feature = "stdarch_arm_dsp", issue = "117237")]

/// ARM-specific 32-bit wide vector of two packed `i16`.
#[unstable(feature = "stdarch_arm_dsp", issue = "117237")]
pub struct int16x2_t(i16, i16);
pub struct int16x2_t(2 x i16);
/// ARM-specific 32-bit wide vector of two packed `u16`.
#[unstable(feature = "stdarch_arm_dsp", issue = "117237")]
pub struct uint16x2_t(u16, u16);
pub struct uint16x2_t(2 x u16);
}

extern "unadjusted" {
Expand Down
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