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Fixing builds
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ryan-summers committed Feb 26, 2024
1 parent 6de076b commit 610aded
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Showing 3 changed files with 10 additions and 9 deletions.
11 changes: 6 additions & 5 deletions src/control_pipe.rs
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
pub fn handle_setup(&mut self) -> Option<Request> {
let count = match self.ep_out.read(&mut self.buf[..]) {
Ok(count) => {
usb_trace!("Read {count} bytes on EP0-OUT: {:?}", &self.buf[..count]);
usb_trace!("Read {} bytes on EP0-OUT: {:?}", count, &self.buf[..count]);
count
}
Err(UsbError::WouldBlock) => return None,
Expand All @@ -91,7 +91,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
// a stalled state.
self.ep_out.unstall();

usb_debug!("EP0 request received: {req:?}");
usb_debug!("EP0 request received: {:?}", req);

/*sprintln!("SETUP {:?} {:?} {:?} req:{} val:{} idx:{} len:{} {:?}",
req.direction, req.request_type, req.recipient,
Expand Down Expand Up @@ -145,13 +145,14 @@ impl<B: UsbBus> ControlPipe<'_, B> {
};

usb_trace!(
"Read {count} bytes on EP0-OUT: {:?}",
"Read {} bytes on EP0-OUT: {:?}",
count,
&self.buf[i..(i + count)]
);
self.i += count;

if self.i >= self.len {
usb_debug!("Request OUT complete: {req:?}");
usb_debug!("Request OUT complete: {:?}", req);
self.state = ControlState::CompleteOut;
return Some(req);
}
Expand Down Expand Up @@ -232,7 +233,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
// There isn't much we can do if the write fails, except to wait for another poll or for
// the host to resend the request.
Err(_err) => {
usb_debug!("Failed to write EP0: {_err:?}");
usb_debug!("Failed to write EP0: {:?}", _err);
return;
}
};
Expand Down
6 changes: 3 additions & 3 deletions src/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -259,21 +259,21 @@ impl<B: UsbBus> UsbDevice<'_, B> {
for i in 1..MAX_ENDPOINTS {
if (ep_setup & bit) != 0 {
for cls in classes.iter_mut() {
usb_trace!("Handling EP{i}-SETUP");
usb_trace!("Handling EP{}-SETUP", i);
cls.endpoint_setup(EndpointAddress::from_parts(
i,
UsbDirection::Out,
));
}
} else if (ep_out & bit) != 0 {
usb_trace!("Handling EP{i}-OUT");
usb_trace!("Handling EP{}-OUT", i);
for cls in classes.iter_mut() {
cls.endpoint_out(EndpointAddress::from_parts(i, UsbDirection::Out));
}
}

if (ep_in_complete & bit) != 0 {
usb_trace!("Handling EP{i}-IN");
usb_trace!("Handling EP{}-IN", i);
for cls in classes.iter_mut() {
cls.endpoint_in_complete(EndpointAddress::from_parts(
i,
Expand Down
2 changes: 1 addition & 1 deletion src/macros.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#[cfg(feature = "log")]
#[cfg(all(feature = "log", not(feature = "defmt")))]
macro_rules! usb_log {
(trace, $($arg:expr),*) => { log::trace!($($arg),*) };
(debug, $($arg:expr),*) => { log::trace!($($arg),*) };
Expand Down

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