Use CCR0 instead of CCR1

rtic-rs · Jul 5, 2024 · ed6c1e8 · ed6c1e8
1 parent b474fee
commit ed6c1e8
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/rtic-monotonics/src/stm32.rs b/rtic-monotonics/src/stm32.rs
@@ -240,8 +240,8 @@ macro_rules! make_timer {
                 $timer.dier().modify(|r| r.set_uie(true));
 
                 // Configure and enable half-period interrupt
-                $timer.ccr(1).write(|r| r.set_ccr(($bits::MAX - ($bits::MAX >> 1)).into()));
-                $timer.dier().modify(|r| r.set_ccie(1, true));
+                $timer.ccr(0).write(|r| r.set_ccr(($bits::MAX - ($bits::MAX >> 1)).into()));
+                $timer.dier().modify(|r| r.set_ccie(0, true));
 
                 // Trigger an update event to load the prescaler value to the clock.
                 $timer.egr().write(|r| r.set_ug(true));
@@ -290,7 +290,7 @@ macro_rules! make_timer {
                     0
                 };
 
-                $timer.ccr(1).write(|r| r.set_ccr(val.into()));
+                $timer.ccr(0).write(|r| r.set_ccr(val.into()));
             }
 
             fn clear_compare_flag() {
@@ -309,8 +309,8 @@ macro_rules! make_timer {
                     assert!(prev % 2 == 1, "Monotonic must have missed an interrupt!");
                 }
                 // Half period
-                if $timer.sr().read().ccif(1) {
-                    $timer.sr().modify(|r| r.set_ccif(1, false));
+                if $timer.sr().read().ccif(0) {
+                    $timer.sr().modify(|r| r.set_ccif(0, false));
                     let prev = $overflow.fetch_add(1, Ordering::Relaxed);
                     assert!(prev % 2 == 0, "Monotonic must have missed an interrupt!");
                 }