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SystemVerilog frontend for Yosys

C++ 69 8 Updated Jan 21, 2025

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog 306 75 Updated Jan 21, 2025

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

Verilog 54 4 Updated Apr 14, 2024
C++ 31 2 Updated Jan 7, 2025

The best source for dashboard icons.

Python 5,326 577 Updated Jan 12, 2025

Video editing with Python

Python 12,923 1,630 Updated Jan 22, 2025

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

C 41 8 Updated Jun 23, 2024

Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

44 3 Updated Mar 22, 2022

Xilinx Embedded Software (embeddedsw) Development

HTML 977 1,076 Updated Dec 3, 2024

Runtime-First FPGA Interchange Routing Contest @ FPGA’24

Python 31 10 Updated Nov 5, 2024

Quickly find differences and similarities in disassembled code

Java 2,368 150 Updated Jan 13, 2025

Python bindings for slang, a library for compiling SystemVerilog

Python 55 9 Updated Jan 18, 2025

SystemVerilog synthesis tool

Verilog 176 23 Updated Jan 22, 2025

Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more

Shell 12 3 Updated Nov 24, 2024

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

C 150 21 Updated Nov 20, 2024

Determines the modules declared and instantiated in a SystemVerilog file

Rust 42 5 Updated Sep 23, 2024

Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7

Shell 64 7 Updated Jun 21, 2024

Rich is a Python library for rich text and beautiful formatting in the terminal.

Python 50,417 1,766 Updated Dec 2, 2024

A utility-first CSS framework for rapid UI development.

TypeScript 84,687 4,292 Updated Jan 22, 2025

FOSS Flow For FPGA

Python 368 49 Updated Jan 6, 2025

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

VHDL 46 11 Updated Dec 6, 2023

Cyclone V bitstream reverse-engineering project

HTML 115 15 Updated Oct 19, 2023

What the f*ck Python? 😱

Python 35,968 2,665 Updated Jan 16, 2025

CORE-V Family of RISC-V Cores

216 16 Updated Feb 15, 2024

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VHDL 130 18 Updated Dec 7, 2024

Tool for shell commands execution, visualization and alerting. Configured with a simple YAML file.

Go 13,042 588 Updated Feb 22, 2024

Python script to transform a VCD file to wavedrom format

Python 75 7 Updated Aug 18, 2022
Python 13 13 Updated Dec 12, 2024
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