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added some fpu instructions #4

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added some fpu instructions #4

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88cdd9c
added some fpu instructions
kolyandex Sep 7, 2023
340c4f2
ftoi
kolyandex Sep 7, 2023
d3558a6
Update m32r.ldefs
kolyandex Sep 7, 2023
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Empty file added Module.manifest
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6 changes: 6 additions & 0 deletions data/languages/m32r.cspec
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,12 @@
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="4" extension="inttype">
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8 changes: 4 additions & 4 deletions data/languages/m32r.ldefs
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Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
<?xml version="1.0" encoding="UTF-8"?>

<language_definitions>
<language processor="M32R"
<language processor="m32r"
endian="big"
size="32"
variant="default"
variant="cc32r"
version="1.0"
slafile="m32r.sla"
processorspec="m32r.pspec"
id="m32r:2:default">
id="m32r:BE:32:cc32r">
<description>m32r</description>
<compiler name="default" spec="m32r.cspec" id="default"/>
<compiler name="cc32r" spec="m32r.cspec" id="cc32r"/>
</language>
</language_definitions>
56 changes: 45 additions & 11 deletions data/languages/m32r.sinc
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Expand Up @@ -85,7 +85,48 @@ FPREL_2: rel is rel16 [ rel = rel16 + 0x80c000; ] { export *:2 rel; }
FP_ADDRESS: rel is rel16 [ rel = rel16 + 0x80c000; ] { export &:4 rel; }


#:FCMPE
#:FMADD
#:FMSUB
#:FTOS

:UTOF Rdest, Rsrc is op3=13 & Rsrc; op12=0x00; op1=4 & Rdest; op12=0x40 {
Rdest = int2float(Rsrc & 0x7FFFFFFF);
}
:ITOF Rdest, Rsrc is op3=13 & Rsrc; op12=0x00; op1=4 & Rdest; op12=0x00 {
Rdest = int2float(Rsrc);
}
:FTOI Rdest, Rsrc is op3=13 & Rsrc; op12=0x00; op1=4 & Rdest; op12=0x80 {
Rdest = trunc(Rsrc);
}

:FCMP Rdest, Rsrc, Rsrc2 is op3=13 & Rsrc; op3=0 & Rsrc2; op1=0 & Rdest; op12=0xC0 {
if (Rsrc f== Rsrc2) goto <eq>;
if (Rsrc f> Rsrc2) goto <gr>;
if (Rsrc f< Rsrc2) goto <le>;
<eq>
Rdest = 0;
goto <end>;
<gr>
Rdest = 1;
goto <end>;
<le>
Rdest = -1;
goto <end>;
<end>
}
:FSUB Rdest, Rsrc, Rsrc2 is op3=13 & Rsrc; op3=0 & Rsrc2; op1=0 & Rdest; op12=0x40 {
Rdest = Rsrc f- Rsrc2;
}
:FADD Rdest, Rsrc, Rsrc2 is op3=13 & Rsrc; op3=0 & Rsrc2; op1=0 & Rdest; op12=0x00 {
Rdest = Rsrc f+ Rsrc2;
}
:FDIV Rdest, Rsrc, Rsrc2 is op3=13 & Rsrc; op3=0 & Rsrc2; op1=2 & Rdest; op12=0x00 {
Rdest = Rsrc f/ Rsrc2;
}
:FMUL Rdest, Rsrc, Rsrc2 is op3=13 & Rsrc; op3=0 & Rsrc2; op1=1 & Rdest; op12=0x00 {
Rdest = Rsrc f* Rsrc2;
}
:ADD Rdest, Rsrc is op1=0 & Rdest; op3=10 & Rsrc {
Rdest = Rdest + Rsrc;
}
Expand Down Expand Up @@ -275,17 +316,7 @@ FP_ADDRESS: rel is rel16 [ rel = rel16 + 0x80c000; ] { export &:4 rel; }
Rdest = Rdest / Rsrc;
}

#:FADD
#:FCMP
#:FCMPE
#:FDIV
#:FMADD
#:FMSUB
#:FMUL
#:FSUB
#:FTOI
#:FTOS
#:ITOF


:JL Rsrc is op12=0x1E; op3=12 & Rsrc {
R14 = (inst_start & 0xFFFFFFFC) + 4;
Expand All @@ -299,6 +330,9 @@ FP_ADDRESS: rel is rel16 [ rel = rel16 + 0x80c000; ] { export &:4 rel; }
}

# Alias for: JMP R14
:RET_NOP is op12=0x1F; op34=0xCE; op12=0xF0; op34=0x00 {
return [R14];
}
:RET is op12=0x1F; op34=0xCE {
return [R14];
}
Expand Down
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