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Update supported ruby version #106

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merged 1 commit into from
Dec 28, 2024
+106 −112
Merged

Update supported ruby version #106

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2 changes: 1 addition & 1 deletion .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ jobs:

strategy:
matrix:
ruby: ['3.3', '3.2', '3.1', '3.0']
ruby: ['3.4', '3.3', '3.2', '3.1']
frozen_string_literal: ['yes', 'no']

env:
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10 changes: 5 additions & 5 deletions lib/rggen/systemverilog/common/feature.rb
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Expand Up @@ -38,9 +38,9 @@ def post_initialize
@package_imports = Hash.new { |h, k| h[k] = [] }
end

def define_entity(context, name, args, &block)
def define_entity(context, name, args, &)
layer, attributes = parse_entity_arguments(args)
entity = create_entity(context, name, attributes, &block)
entity = create_entity(context, name, attributes, &)
add_entity(context, entity, name, layer)
end

Expand All @@ -56,9 +56,9 @@ def parse_entity_arguments(args)
end
end

def create_entity(context, name, attributes, &block)
merged_attributes = { name: name }.merge(Hash(attributes))
__send__(context.method_name, context.entity_type, merged_attributes, &block)
def create_entity(context, name, attributes, &)
merged_attributes = { name: }.merge(Hash(attributes))
__send__(context.method_name, context.entity_type, merged_attributes, &)
end

def add_entity(context, entity, name, layer)
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4 changes: 2 additions & 2 deletions lib/rggen/systemverilog/common/utility.rb
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Expand Up @@ -92,7 +92,7 @@ def width_cast(expression, width)
end

def argument(name, attribute = {})
DataObject.new(:argument, attribute.merge(name: name)).declaration
DataObject.new(:argument, attribute.merge(name:)).declaration
end

{
Expand All @@ -103,7 +103,7 @@ def argument(name, attribute = {})
package_definition: PackageDefinition
}.each do |method_name, definition|
define_method(method_name) do |name, attributes = {}, &block|
definition.new(attributes.merge(name: name), &block).to_code
definition.new(attributes.merge(name:), &block).to_code
end
end
end
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4 changes: 2 additions & 2 deletions lib/rggen/systemverilog/common/utility/structure_definition.rb
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Expand Up @@ -7,9 +7,9 @@ module Utility
class StructureDefinition < Core::Utility::CodeUtility::StructureDefinition
include Core::Utility::AttributeSetter

def initialize(default_attributes = {}, &block)
def initialize(default_attributes = {}, &)
apply_attributes(**default_attributes)
super(&block)
super(&)
end

private
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10 changes: 5 additions & 5 deletions lib/rggen/systemverilog/ral/bit_field/type.rb
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Expand Up @@ -4,12 +4,12 @@
sv_ral do
base_feature do
define_helpers do
def access(access_type = nil, &block)
attribute_accessor('@access', access_type, &block)
def access(access_type = nil, &)
attribute_accessor('@access', access_type, &)
end

def model_name(name = nil, &block)
attribute_accessor('@model_name', name, &block)
def model_name(name = nil, &)
attribute_accessor('@model_name', name, &)
end

private
Expand All @@ -28,7 +28,7 @@ def attribute_accessor(variable_name, value, &block)
build do
variable :ral_model, {
name: bit_field.name, data_type: model_name,
array_size: array_size, random: true
array_size:, random: true
}
end

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10 changes: 4 additions & 6 deletions lib/rggen/systemverilog/ral/feature.rb
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Expand Up @@ -6,14 +6,12 @@ module RAL
class Feature < Common::Feature
private

def create_variable(_, attributes, &block)
DataObject.new(
:variable, attributes.merge(array_format: :unpacked), &block
)
def create_variable(_, attributes, &)
DataObject.new(:variable, attributes.merge(array_format: :unpacked), &)
end

def create_parameter(_, attributes, &block)
DataObject.new(:parameter, attributes, &block)
def create_parameter(_, attributes, &)
DataObject.new(:parameter, attributes, &)
end

define_entity :variable, :create_variable, :variable, -> { component.parent }
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26 changes: 13 additions & 13 deletions lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
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Expand Up @@ -5,47 +5,47 @@
build do
if external_read_data?
input :value_in, {
name: "i_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}", width:,
array_size:, array_format: array_port_format
}
else
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end
if bit_field.hw_write?
input :hw_write_enable, {
name: "i_#{full_name}_hw_write_enable", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
input :hw_write_data, {
name: "i_#{full_name}_hw_write_data", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}_hw_write_data", width:,
array_size:, array_format: array_port_format
}
end
if bit_field.hw_set?
input :hw_set, {
name: "i_#{full_name}_hw_set", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}_hw_set", width:,
array_size:, array_format: array_port_format
}
end
if bit_field.hw_clear?
input :hw_clear, {
name: "i_#{full_name}_hw_clear", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}_hw_clear", width:,
array_size:, array_format: array_port_format
}
end
if bit_field.write_trigger?
output :write_trigger, {
name: "o_#{full_name}_write_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
if bit_field.read_trigger?
output :read_trigger, {
name: "o_#{full_name}_read_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
end
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12 changes: 6 additions & 6 deletions lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
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Expand Up @@ -4,17 +4,17 @@
sv_rtl do
build do
input :set, {
name: "i_#{full_name}_set", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}_set", width:,
array_size:, array_format: array_port_format
}
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
if bit_field.reference?
output :value_unmasked, {
name: "o_#{full_name}_unmasked", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}_unmasked", width:,
array_size:, array_format: array_port_format
}
end
end
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6 changes: 3 additions & 3 deletions lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
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Expand Up @@ -5,14 +5,14 @@
build do
unless bit_field.reference?
input :value_in, {
name: "i_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end
if rotrg?
output :read_trigger, {
name: "o_#{full_name}_read_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
end
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10 changes: 5 additions & 5 deletions lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
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Expand Up @@ -6,16 +6,16 @@
unless bit_field.reference?
input :valid, {
name: "i_#{full_name}_valid", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
input :value_in, {
name: "i_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}", width:,
array_size:, array_format: array_port_format
}
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end

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8 changes: 4 additions & 4 deletions lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
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Expand Up @@ -5,13 +5,13 @@
build do
unless bit_field.reference?
input :value_in, {
name: "i_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end
output :trigger, {
name: "o_#{full_name}_trigger", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}_trigger", width:,
array_size:, array_format: array_port_format
}
end

Expand Down
12 changes: 6 additions & 6 deletions lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
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Expand Up @@ -4,23 +4,23 @@
sv_rtl do
build do
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
unless bit_field.reference?
input :value_in, {
name: "i_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end
if rowotrg?
output :write_trigger, {
name: "o_#{full_name}_write_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
output :read_trigger, {
name: "o_#{full_name}_read_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
end
Expand Down
8 changes: 4 additions & 4 deletions lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
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Expand Up @@ -4,12 +4,12 @@
sv_rtl do
build do
input :clear, {
name: "i_#{full_name}_clear", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}_clear", width:,
array_size:, array_format: array_port_format
}
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end

Expand Down
8 changes: 4 additions & 4 deletions lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
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Expand Up @@ -4,17 +4,17 @@
sv_rtl do
build do
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
if rwtrg?
output :write_trigger, {
name: "o_#{full_name}_write_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
output :read_trigger, {
name: "o_#{full_name}_read_trigger", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
end
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6 changes: 3 additions & 3 deletions lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
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Expand Up @@ -6,12 +6,12 @@
unless bit_field.reference?
input :clear, {
name: "i_#{full_name}_clear", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end

Expand Down
6 changes: 3 additions & 3 deletions lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
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Expand Up @@ -6,12 +6,12 @@
unless bit_field.reference?
input :control, {
name: "i_#{full_name}_#{enable_or_lock}", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end

Expand Down
10 changes: 5 additions & 5 deletions lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
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Expand Up @@ -6,16 +6,16 @@
unless bit_field.reference?
input :valid, {
name: "i_#{full_name}_valid", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
input :value_in, {
name: "i_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "i_#{full_name}", width:,
array_size:, array_format: array_port_format
}
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end

Expand Down
6 changes: 3 additions & 3 deletions lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
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Expand Up @@ -6,12 +6,12 @@
unless bit_field.reference?
input :set, {
name: "i_#{full_name}_set", width: 1,
array_size: array_size, array_format: array_port_format
array_size:, array_format: array_port_format
}
end
output :value_out, {
name: "o_#{full_name}", width: width,
array_size: array_size, array_format: array_port_format
name: "o_#{full_name}", width:,
array_size:, array_format: array_port_format
}
end

Expand Down
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