change indirect index logic (#105, rggen/rggen#224)

lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -8,26 +8,55 @@ module IndirectIndex
 
         def index_fields
           @index_fields ||=
-            register.collect_index_fields(register_block.bit_fields)
+            register
+              .collect_index_fields(register_block.bit_fields)
         end
 
-        def index_width
-          @index_width ||= index_fields.sum(&:width)
+        def index_match_width
+          index_fields.size
         end
 
         def index_values
+          @index_values ||= collect_index_values
+        end
+
+        def collect_index_values
           loop_variables = register.local_loop_variables
           register.index_entries.zip(index_fields).map do |entry, field|
             if entry.array_index?
-              loop_variables.shift[0, field.width]
+              array_index_value(loop_variables.shift, field.width)
             else
-              hex(entry.value, field.width)
+              fixed_index_value(entry.value, field.width)
             end
           end
         end
 
-        def indirect_index_assignment
-          assign(indirect_index, concat(index_fields.map(&:value)))
+        def array_index_value(value, width)
+          "#{width}'(#{value})"
+        end
+
+        def fixed_index_value(value, width)
+          hex(value, width)
+        end
+
+        def indirect_index_matches(code)
+          index_fields.each_with_index do |field, i|
+            rhs = index_match_rhs(i)
+            lhs = index_match_lhs(field.value, index_values[i])
+            code << assign(rhs, lhs) << nl
+          end
+        end
+
+        def index_match_rhs(index)
+          if index_match_width == 1
+            indirect_match
+          else
+            indirect_match[index]
+          end
+        end
+
+        def index_match_lhs(field, value)
+          "#{field} == #{value}"
         end
       end
     end

lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -6,12 +6,11 @@ rggen_indirect_register #(
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
   .VALUE_WIDTH          (<%= value_width %>),
-  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
-  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+  .INDIRECT_MATCH_WIDTH (<%= index_match_width %>)
 ) u_register (
   .i_clk            (<%= register_block.clock %>),
   .i_rst_n          (<%= register_block.reset %>),
   .register_if      (<%= register_if %>),
-  .i_indirect_index (<%= indirect_index %>),
+  .i_indirect_match (<%= indirect_match %>),
   .bit_field_if     (<%= bit_field_if %>)
 );

lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -5,11 +5,11 @@
     include RgGen::SystemVerilog::RTL::IndirectIndex
 
     build do
-      logic :indirect_index, { width: index_width }
+      logic :indirect_match, { width: index_match_width }
     end
 
     main_code :register do |code|
-      code << indirect_index_assignment << nl
+      indirect_index_matches(code)
       code << process_template
     end
   end

spec/rggen/systemverilog/rtl/register/sv_rtl_top_spec.rb

@@ -453,10 +453,11 @@ def create_registers(&body)
           genvar j;
           for (i = 0;i < 2;++i) begin : g
             for (j = 0;j < 2;++j) begin : g
-              logic [3:0] indirect_index;
+              logic [1:0] indirect_match;
               rggen_bit_field_if #(32) bit_field_if();
               `rggen_tie_off_unused_signals(32, 32'h00000303, bit_field_if)
-              assign indirect_index = {register_if[0].value[0+:2], register_if[0].value[8+:2]};
+              assign indirect_match[0] = register_if[0].value[0+:2] == 2'(i);
+              assign indirect_match[1] = register_if[0].value[8+:2] == 2'(j);
               rggen_indirect_register #(
                 .READABLE             (1),
                 .WRITABLE             (1),
@@ -465,13 +466,12 @@ def create_registers(&body)
                 .BUS_WIDTH            (32),
                 .DATA_WIDTH           (32),
                 .VALUE_WIDTH          (32),
-                .INDIRECT_INDEX_WIDTH (4),
-                .INDIRECT_INDEX_VALUE ({i[0+:2], j[0+:2]})
+                .INDIRECT_MATCH_WIDTH (2)
               ) u_register (
                 .i_clk            (i_clk),
                 .i_rst_n          (i_rst_n),
                 .register_if      (register_if[8+2*i+j]),
-                .i_indirect_index (indirect_index),
+                .i_indirect_match (indirect_match),
                 .bit_field_if     (bit_field_if)
               );
               if (1) begin : g_bit_field_0