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Restyled by verible
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restyled-commits committed Sep 15, 2023
1 parent 8692e94 commit b012fcd
Showing 1 changed file with 10 additions and 10 deletions.
20 changes: 10 additions & 10 deletions verible-test-0.sv
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
module debounce(
input wire logic clk, output logic debounced
);
stateType ns;
module debounce (
input wire logic clk,
output logic debounced
);
stateType ns;

always_comb
begin
ns = ERR;
end
always_comb begin
ns = ERR;
end

logic timerDone;
logic clrTimer;
endmodule
logic clrTimer;
endmodule

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