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Add a bunch of pictures for my slides
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@VonTum
VonTum committed Jul 30, 2024
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2 changes: 2 additions & 0 deletions README.md
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Expand Up @@ -13,6 +13,8 @@ To use the accompanying VSCode Extension for Syntax Highlighting and Code Sugges
ext install LennartVanHirtum.sus-lsp
```

For an example project to tinker with, see [VonTum/BitSerialMatrixMultiply](https://github.com/VonTum/BitSerialMatrixMultiply).

## Core philosophy

SUS is meant to be a direct competitor to Synthesizeable Verilog and VHDL. Its main goal is to be an intuitive and thin syntax for building netlists, such that traditional synthesis tools can still be used to analyze the resulting hardware. SUS shall impose no paradigm on the hardware designer, such as requiring specific communication protocols or iteration constructs. In other words, SUS is not there to abstract away complexity, but rather to make the inherent complexity of hardware design more manageable.
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5 changes: 2 additions & 3 deletions bitSerialMatrixMultiply.sus
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Expand Up @@ -42,12 +42,11 @@ module BitSerialMatrixMultiply {
module BitSerialMatrixMultiplyTemplate {
input gen int WIDTH
input gen int HEIGHT
input gen int[WIDTH][HEIGHT] MATRIX

// 32 right now, because ints are't sized yet.
gen int INT_BITWIDTH = 32

input gen int[WIDTH][HEIGHT] MATRIX

BitSerialMatrixMultiplyState::<WIDTH, HEIGHT, MATRIX;> bsm_state

interface BitSerialMatrixMultiplyTemplate : bool start, int[WIDTH] values -> int[HEIGHT] result
Expand All @@ -59,7 +58,7 @@ module BitSerialMatrixMultiplyTemplate {
// Explicitly not use value
int _ = iter.value

// This is above start, so start has write priority on split_into_bits. TODO shift down once we have `overwrite`
// This is above start, so start has write priority on split_into_bits.
if iter.valid {
// It's a shift register
for int BIT in 1..INT_BITWIDTH {
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31 changes: 31 additions & 0 deletions philosophy/images/multipleInterfaces.drawio
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