Add extern & __builtin__

README.md

@@ -150,11 +150,12 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Generative For Loops
 - [ ] Generative While Loops
 - [x] Generative Parameters
+- [ ] Generative Default Arguments
 - [x] Type Parameters
 - [ ] Generative Asserts
 - [x] Multi-Interface Syntax
-- [ ] Native Module integration syntax
-- [ ] Intrinsic Modules
+- [x] Native Module integration syntax
+- [x] Intrinsic Modules
 - [x] Can Parse FIFO implementation
 - [ ] Clock Domain Crossings
 - [ ] Rhythm Syntax
@@ -187,10 +188,10 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Indeterminable port latency
 - [x] Latency Counting uses latency specifiers
 - [x] Latency for output-only modules
-- [x] Latency Counting is invariant across arbitrary algorithm starting nodes
+- [x] Latency Counting is invariant across arbitrary algorithm starting nodes (not quite, some starting nodes may error. But those that don't are equivalent!)
 - [x] Integrate into Verilog generation
-- [ ] Latency cuts
-- [ ] Latency Offset
+- [x] Latency cuts
+- [x] Latency Offset
 - [ ] Latency Cuts & Latency Counting for "disjoint Input-Output blocks"
 - [ ] Split Latencies
 

core.sus

@@ -1,26 +1,21 @@
 
 // Compiler Intrinsic
-module LatencyOffset<T> {
+__builtin__ module LatencyOffset<T> {
     input gen int OFFSET
     interface LatencyOffset : T in'0 -> T out'OFFSET
-
-    // action start : (bool do_start) {
-    // }
-    // query pop : (bool do_pop), -> bool valid, T data {}
-    // trigger iter : -> bool valid
 }
 
 // Compiler Intrinsic
-module CrossDomain<T> {
+__builtin__ module CrossDomain<T> {
     interface in_domain : T in'0
     domain out
-    interface out_domain : T out'0
+    interface out_domain : -> T out'0
 }
 
-module IntToBits {
+__builtin__ module IntToBits {
     interface IntToBits : int value'0 -> bool[32] bits'0
 }
 
-module BitsToInt {
+__builtin__ module BitsToInt {
     interface IntToBits : bool[32] bits'0 -> int value'0
 }