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Remove support for Zicond; switch to xtheadcondmov
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The `Zicond` extension ends up producing pretty bad code. For example,
the following piece of code:

```
fn func(a0: u32, a1: u32, a2: u32) -> u32 {
    if a0 == 0 {
        a1
    } else {
        a2
    }
}
```

with `Zicond` produces *two* conditional moves and one `or`, while
with the `xtheadcondmov` it is a single conditional move and
a register to register move, as you'd expect.

The `Zicond` might be more in-line with RISC-V's philosophy of not
requiring more than two read ports per instruction, but we really
don't care, and this *does* produce a measurable and significant
performance difference.
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koute committed Feb 21, 2024
1 parent 6eac0e7 commit 37c6397
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Showing 10 changed files with 295 additions and 174 deletions.
15 changes: 13 additions & 2 deletions crates/polkavm-common/src/program.rs
Original file line number Diff line number Diff line change
Expand Up @@ -673,6 +673,9 @@ define_opcodes! {
branch_less_signed = 48,
branch_greater_or_equal_unsigned = 41,
branch_greater_or_equal_signed = 43,

cmov_if_zero_imm = 85,
cmov_if_not_zero_imm = 86,
]

// Instructions with args: reg, reg, reg
Expand Down Expand Up @@ -978,11 +981,19 @@ impl<'a> InstructionVisitor for core::fmt::Formatter<'a> {
}

fn cmov_if_zero(&mut self, d: Reg, s: Reg, c: Reg) -> Self::ReturnTy {
write!(self, "{d} = ({c} == 0) ? {s} : 0")
write!(self, "{d} = {s} if {c} == 0")
}

fn cmov_if_not_zero(&mut self, d: Reg, s: Reg, c: Reg) -> Self::ReturnTy {
write!(self, "{d} = ({c} != 0) ? {s} : 0")
write!(self, "{d} = {s} if {c} != 0")
}

fn cmov_if_zero_imm(&mut self, d: Reg, c: Reg, s: u32) -> Self::ReturnTy {
write!(self, "{d} = {s} if {c} == 0")
}

fn cmov_if_not_zero_imm(&mut self, d: Reg, c: Reg, s: u32) -> Self::ReturnTy {
write!(self, "{d} = {s} if {c} != 0")
}

fn add_imm(&mut self, d: Reg, s1: Reg, s2: u32) -> Self::ReturnTy {
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