Embedding changes for multi-bit constants in design-edit

[behzadmehmood]

Motivate of the pull request

• To address an existing issue. If so, please add GH or Jira ID here: https://github.com/os-fpga/Jira_Testcase/tree/main/EDA-3307
• Breaking new feature. If so, please describe details in the description part.

Which submodule does this change impact ?

• Backend
• FOEDAG_rs
• IP_Catalog
• Raptor_Tools
• yosys_verific_rs
• zephyr-rapidsi-dev
• Github CI

What does this pull request change?

Designs with multi-bit constants on IO primitives' port connections were not supported by netlist editing tool. This PR adds this support.

Verified that the following tests passed locally before PR was created.

• make tests/batch_all
• Describe or list testcases run specifically to verify these updates if not covered above.

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.