Latest Release_Sim_1.6.0

[AYYAZmayo]

Motivate of the pull request

• To address an existing issue. If so, please add GH or Jira ID here:
• Breaking new feature. If so, please describe details in the description part.

Which submodule does this change impact ?

• Backend
• FOEDAG_rs
• IP_Catalog
• Raptor_Tools
• yosys_verific_rs
• zephyr-rapidsi-dev
• Github CI

What does this pull request change?

Bump Latest RS_FPGA_PRIMITVIES Release_SIM_1.6.0

Verified that the following tests passed locally before PR was created.

• make tests/batch_all
• Describe or list testcases run specifically to verify these updates if not covered above.

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[AYYAZmayo]

@bilal458 Closing the PR as PNR simulations are failing in CI on Icarus with latest addition of 'specify endspecify blocks' in LUTx primitives. Please fix it. So reverting the PR.

[bilal458]

@moinijaz can we fix this or this needs to go to Hardware.