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[nrf fromlist] arch: riscv: option to init custom hw stacked esf memb… #2432

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[nrf fromlist] arch: riscv: option to init custom hw stacked esf memb… #2432

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5 changes: 5 additions & 0 deletions arch/riscv/Kconfig
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Expand Up @@ -83,6 +83,11 @@ config RISCV_SOC_HAS_ISR_STACKING
saved on the stack by the hardware, and the registers saved by the
software macros. The structure must be called 'struct arch_esf'.

- SOC_ISR_STACKING_ESR_INIT: macro guarded by !_ASMLANGUAGE.
Some hardware stacked registers should be initialized on init
stack with proper values. This prevents from incorrect behavior
on entry context switch when initial stack is restored.

config RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
bool
help
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4 changes: 4 additions & 0 deletions arch/riscv/core/thread.c
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Expand Up @@ -106,6 +106,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->soc_context = soc_esf_init;
#endif

#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
SOC_ISR_STACKING_ESR_INIT;
#endif

thread->callee_saved.sp = (unsigned long)stack_init;

/* where to go when returning from z_riscv_switch() */
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7 changes: 7 additions & 0 deletions soc/nordic/common/vpr/soc_isr_stacking.h
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Expand Up @@ -62,6 +62,13 @@

#endif /* DT_PROP(VPR_CPU, nordic_bus_width) == 64 */

/*
* VPR stacked mcause needs to have proper value on initial stack.
* Initial mret will restore this value.
*/
#define SOC_ISR_STACKING_ESR_INIT \
stack_init->_mcause = 0;

Check notice on line 71 in soc/nordic/common/vpr/soc_isr_stacking.h

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soc/nordic/common/vpr/soc_isr_stacking.h:71 
-#define SOC_ISR_STACKING_ESR_INIT                                                                  \
-	stack_init->_mcause = 0;
+#define SOC_ISR_STACKING_ESR_INIT stack_init->_mcause = 0;
#else /* _ASMLANGUAGE */

/*
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