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[backport-ncs2.6][nrf fromtree] drivers: pinctrl_nrf: Configure QSPI IO3 pin as output… #1628

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anangl
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@anangl anangl commented Apr 11, 2024

… set high

... so that the pin is kept in a defined state when the IO3 line is not controlled by the QSPI peripheral (when the peripheral is disabled or disconnected from the pin).

The IO3 pin in Quad SPI flash chips usually has dual functionality - it is an I/O line when the chip is configured to work in Quad (4 I/O) mode and it is a HOLD# or RESET# line when the chip is configured to work in non-Quad (2 I/O) mode. In the latter case, it is important that the line is kept in the inactive (high) state, otherwise communication with the chip may be disrupted (and this actually happens when e.g. the spi_flash sample is used on a brand new nRF5340 or nRF52840 DK - the nrf_qspi_nor driver fails to initialize and the sample just ends up with the "mx25r6435f@0: device not ready" message).

This commit addresses the problem in the same way that it was done for the CSN line in commit 6d8172f.

Signed-off-by: Andrzej Głąbek [email protected]

Upstream PR: zephyrproject-rtos/zephyr#71373

@NordicBuilder NordicBuilder requested a review from gmarull April 11, 2024 14:43
@anangl anangl changed the title [backport-ncs2.5][nrf fromlist] drivers: pinctrl_nrf: Configure QSPI IO3 pin as output… [backport-ncs2.6][nrf fromlist] drivers: pinctrl_nrf: Configure QSPI IO3 pin as output… Apr 11, 2024
@mariusz-nordicsemi mariusz-nordicsemi added this to the ncs-2.6.1 milestone Apr 17, 2024
@anangl anangl force-pushed the fix_qspi_io3_gpio_cfg_ncs26 branch from f53c74d to f502c9e Compare April 17, 2024 13:15
@anangl anangl changed the title [backport-ncs2.6][nrf fromlist] drivers: pinctrl_nrf: Configure QSPI IO3 pin as output… [backport-ncs2.6][nrf fromtree] drivers: pinctrl_nrf: Configure QSPI IO3 pin as output… Apr 17, 2024
@anangl anangl force-pushed the fix_qspi_io3_gpio_cfg_ncs26 branch from f502c9e to 3ff991c Compare April 18, 2024 07:42
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anangl commented Apr 18, 2024

Rebased.

… set high

... so that the pin is kept in a defined state when the IO3 line is
not controlled by the QSPI peripheral (when the peripheral is disabled
or disconnected from the pin).

The IO3 pin in Quad SPI flash chips usually has dual functionality -
it is an I/O line when the chip is configured to work in Quad (4 I/O)
mode and it is a HOLD# or RESET# line when the chip is configured to
work in non-Quad (2 I/O) mode. In the latter case, it is important that
the line is kept in the inactive (high) state, otherwise communication
with the chip may be disrupted (and this actually happens when e.g.
the spi_flash sample is used on a brand new nRF5340 or nRF52840 DK -
the nrf_qspi_nor driver fails to initialize and the sample just ends
up with the "mx25r6435f@0: device not ready" message).

This commit addresses the problem in the same way that it was done for
the CSN line in commit 6d8172f.

Signed-off-by: Andrzej Głąbek <[email protected]>
(cherry picked from commit 2f44266)
@anangl anangl force-pushed the fix_qspi_io3_gpio_cfg_ncs26 branch from 3ff991c to fecb6f4 Compare April 22, 2024 08:37
@cvinayak cvinayak merged commit 3758bcb into nrfconnect:v3.5.99-ncs1-branch Apr 22, 2024
8 checks passed
@anangl anangl deleted the fix_qspi_io3_gpio_cfg_ncs26 branch April 22, 2024 11:46
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6 participants