fix: address clippy lints

src/cpu/chip8/memory.rs

@@ -11,7 +11,7 @@ where
     T: Default,
 {
     pub fn new(capacity: usize) -> Self {
-        let inner = (0..capacity).into_iter().map(|_| <T>::default()).collect();
+        let inner = (0..capacity).map(|_| <T>::default()).collect();
         Self { capacity, inner }
     }
 }

src/cpu/chip8/operations/mod.rs

@@ -648,7 +648,6 @@ impl<R> Generate<Chip8<R>> for ReadRegistersFromMemory {
     fn generate(&self, cpu: &Chip8<R>) -> Vec<Microcode> {
         let reg_inclusive_end_idx = u8::from(self.addressing_mode.src);
         (0..=reg_inclusive_end_idx)
-            .into_iter()
             .filter(|idx| *idx <= 0x0f)
             // safe to unwrap due to filter constraint
             .map(|idx| GpRegisters::try_from(idx).unwrap())
@@ -685,7 +684,6 @@ impl<R> Generate<Chip8<R>> for StoreRegistersToMemory {
     fn generate(&self, cpu: &Chip8<R>) -> Vec<Microcode> {
         let reg_inclusive_end_idx = u8::from(self.addressing_mode.src);
         (0..=reg_inclusive_end_idx)
-            .into_iter()
             .filter(|idx| *idx <= 0x0f)
             // safe to unwrap due to filter constraint
             .map(|idx| GpRegisters::try_from(idx).unwrap())

src/cpu/chip8/operations/tests/mod.rs

@@ -113,7 +113,6 @@ fn should_generate_drw_instruction() {
     cpu.address_space.write(0x00, 0xf0).unwrap();
 
     let mut expected = (0..8)
-        .into_iter()
         // 0xf0
         .map(|x| {
             let bit_is_set = (0xf0u8 >> (7 - x)) & 1;