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OpenMBMC is a simple to use IP core for HyperBUS like memory devices.

Features:

• Single 32 bit accesses (no bursts), 8 and 16 bit writes are supported
• Works with any FPGA and any type of I/O bank
• Small (less than 300 LUT)
• SLOW: device clock equals system clock divided by 4
• Latency set to minimal, variable latency supported (not for APmemory devices)
• Register auto-init (not for HyperFlash)
• Avalon and AHBLite buses are supported
• IP Catalog ready for: AMD, Altera, and Lattice (Microchip need manual: "Create Core from HDL")

Devices supported:

• HyperRAM (latency set to 3) - tested on real devices
• HyperFlash (latency set to 5) - tested in simulation only
• OPI - support planned