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Correct my leaking ruby-isms
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@maxfierke
maxfierke committed Jan 18, 2024
1 parent ba353ef commit e7eb6ad
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Showing 5 changed files with 130 additions and 130 deletions.
16 changes: 8 additions & 8 deletions cart/mbc/common.go
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Original file line number Diff line number Diff line change
Expand Up @@ -7,14 +7,14 @@ const (
ROM_BANK_SIZE = 0x4000
)

func readBankAddr(memory []byte, banks_region mem.MemRegion, bank_size uint16, current_bank uint16, addr uint16) byte {
bank_base_addr := current_bank * bank_size
bank_slot_addr := addr - banks_region.Start
return memory[bank_base_addr+bank_slot_addr]
func readBankAddr(memory []byte, banksRegion mem.MemRegion, bankSize uint16, currentBank uint16, addr uint16) byte {
bankBaseAddr := currentBank * bankSize
bankSlotAddr := addr - banksRegion.Start
return memory[bankBaseAddr+bankSlotAddr]
}

func writeBankAddr(memory []byte, banks_region mem.MemRegion, bank_size uint16, current_bank uint16, addr uint16, value byte) {
bank_base_addr := current_bank * bank_size
bank_slot_addr := addr - banks_region.Start
memory[bank_base_addr+bank_slot_addr] = value
func writeBankAddr(memory []byte, banksRegion mem.MemRegion, bankSize uint16, currentBank uint16, addr uint16, value byte) {
bankBaseAddr := currentBank * bankSize
bankSlotAddr := addr - banksRegion.Start
memory[bankBaseAddr+bankSlotAddr] = value
}
10 changes: 5 additions & 5 deletions cart/mbc/mbc0.go
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@ import (
)

var (
mbc0_rom_bank = mem.MemRegion{Start: 0x0000, End: 0x7FFF}
mbc0_ram_bank = mem.MemRegion{Start: 0xA000, End: 0xBFFF}
MBC0_ROM_BANK = mem.MemRegion{Start: 0x0000, End: 0x7FFF}
MBC0_RAM_BANK = mem.MemRegion{Start: 0xA000, End: 0xBFFF}
)

type MBC0 struct {
Expand All @@ -20,20 +20,20 @@ func NewMBC0(rom []byte) *MBC0 {
}

func (m *MBC0) OnRead(mmu *mem.MMU, addr uint16) mem.MemRead {
if addr <= mbc0_rom_bank.End {
if addr <= MBC0_ROM_BANK.End {
return mem.ReadReplace(m.rom[addr])
}

return mem.ReadPassthrough()
}

func (m *MBC0) OnWrite(mmu *mem.MMU, addr uint16, value byte) mem.MemWrite {
if addr <= mbc0_rom_bank.End {
if addr <= MBC0_ROM_BANK.End {
// Put the Read-Only in ROM
return mem.WriteBlock()
}

if mbc0_ram_bank.Contains(addr, false) {
if MBC0_RAM_BANK.Contains(addr, false) {
// RAM is RAM and this is a fake cartridge, so...
return mem.WritePassthrough()
}
Expand Down
98 changes: 49 additions & 49 deletions cart/mbc/mbc1.go
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Original file line number Diff line number Diff line change
Expand Up @@ -7,69 +7,69 @@ import (
)

var (
mbc1_rom_bank_x0 = mem.MemRegion{Start: 0x0000, End: 0x3FFF}
mbc1_rom_banks = mem.MemRegion{Start: 0x4000, End: 0x7FFF}
mbc1_ram_banks = mem.MemRegion{Start: 0xA000, End: 0xBFFF}
MBC1_ROM_BANK_X0 = mem.MemRegion{Start: 0x0000, End: 0x3FFF}
MBC1_ROM_BANKS = mem.MemRegion{Start: 0x4000, End: 0x7FFF}
MBC1_RAM_BANKS = mem.MemRegion{Start: 0xA000, End: 0xBFFF}

mbc1_reg_ram_enable = mem.MemRegion{Start: 0x0000, End: 0x1FFF}
mbc1_reg_ram_enable_mask = byte(0xF)
mbc1_reg_ram_enabled = byte(0xA)
MBC1_REG_RAM_ENABLE = mem.MemRegion{Start: 0x0000, End: 0x1FFF}
MBC1_REG_RAM_ENABLE_MASK = byte(0xF)
MBC1_REG_RAM_ENABLED = byte(0xA)

mbc1_reg_rom_bank = mem.MemRegion{Start: 0x2000, End: 0x3FFF}
mbc1_reg_rom_bank_sel_mask = uint16(0x1F)
MBC1_REG_ROM_BANK = mem.MemRegion{Start: 0x2000, End: 0x3FFF}
MBC1_REG_ROM_BANK_SEL_MASK = uint16(0x1F)

mbc1_reg_ram_bank_or_msb_rom_bank = mem.MemRegion{Start: 0x4000, End: 0x5FFF}
mbc1_reg_msb_rom_bank_sel_mask = ^uint16(0x60)
MBC1_REG_RAM_BANK_OR_MSB_ROM_BANK = mem.MemRegion{Start: 0x4000, End: 0x5FFF}
MBC1_REG_MSB_ROM_BANK_SEL_MASK = ^uint16(0x60)

mbc1_reg_bank_mode_sel = mem.MemRegion{Start: 0x6000, End: 0x7FFF}
MBC1_REG_BANK_MODE_SEL = mem.MemRegion{Start: 0x6000, End: 0x7FFF}
)

// Struct for MBC1 support (minus MBC1M, currently)
type MBC1 struct {
cur_ram_bank uint8
cur_rom_bank uint16
ram []byte
ram_enabled bool
ram_selected bool
rom []byte
curRamBank uint8
curRomBank uint16
ram []byte
ramEnabled bool
ramSelected bool
rom []byte
}

func NewMBC1(rom []byte, ram []byte) *MBC1 {
return &MBC1{
cur_ram_bank: 0,
cur_rom_bank: 0,
ram: ram,
ram_enabled: false,
ram_selected: false,
rom: rom,
curRamBank: 0,
curRomBank: 0,
ram: ram,
ramEnabled: false,
ramSelected: false,
rom: rom,
}
}

func (m *MBC1) OnRead(mmu *mem.MMU, addr uint16) mem.MemRead {
if mbc1_rom_bank_x0.Contains(addr, false) {
if MBC1_ROM_BANK_X0.Contains(addr, false) {
return mem.ReadReplace(m.rom[addr])
} else if mbc1_rom_banks.Contains(addr, false) {
} else if MBC1_ROM_BANKS.Contains(addr, false) {
// see https://gbdev.io/pandocs/MBC1.html#00003fff--rom-bank-x0-read-only
romBank := max(m.cur_rom_bank, 1)
romBank := max(m.curRomBank, 1)
if romBank == 0x20 || romBank == 0x40 || romBank == 0x60 {
romBank += 1
}

bankByte := readBankAddr(
m.rom,
mbc1_rom_banks,
MBC1_ROM_BANKS,
ROM_BANK_SIZE,
romBank,
addr,
)
return mem.ReadReplace(bankByte)
} else if mbc1_ram_banks.Contains(addr, false) {
if m.ram_enabled {
} else if MBC1_RAM_BANKS.Contains(addr, false) {
if m.ramEnabled {
bankByte := readBankAddr(
m.ram,
mbc1_ram_banks,
MBC1_RAM_BANKS,
RAM_BANK_SIZE,
uint16(m.cur_ram_bank),
uint16(m.curRamBank),
addr,
)
return mem.ReadReplace(bankByte)
Expand All @@ -83,43 +83,43 @@ func (m *MBC1) OnRead(mmu *mem.MMU, addr uint16) mem.MemRead {
}

func (m *MBC1) OnWrite(mmu *mem.MMU, addr uint16, value byte) mem.MemWrite {
if mbc1_reg_ram_enable.Contains(addr, false) {
if value&mbc1_reg_ram_enable_mask == mbc1_reg_ram_enabled {
m.ram_enabled = true
if MBC1_REG_RAM_ENABLE.Contains(addr, false) {
if value&MBC1_REG_RAM_ENABLE_MASK == MBC1_REG_RAM_ENABLED {
m.ramEnabled = true
} else {
m.ram_enabled = false
m.ramEnabled = false
}

return mem.WriteBlock()
} else if mbc1_reg_rom_bank.Contains(addr, false) {
m.cur_rom_bank =
(m.cur_rom_bank & ^mbc1_reg_rom_bank_sel_mask) |
(uint16(value) & mbc1_reg_rom_bank_sel_mask)
} else if MBC1_REG_ROM_BANK.Contains(addr, false) {
m.curRomBank =
(m.curRomBank & ^MBC1_REG_ROM_BANK_SEL_MASK) |
(uint16(value) & MBC1_REG_ROM_BANK_SEL_MASK)
return mem.WriteBlock()
} else if mbc1_reg_ram_bank_or_msb_rom_bank.Contains(addr, false) {
if m.ram_selected {
m.cur_ram_bank = value & 0x3
} else if MBC1_REG_RAM_BANK_OR_MSB_ROM_BANK.Contains(addr, false) {
if m.ramSelected {
m.curRamBank = value & 0x3
} else {
msb := uint16(value) & 0x3 << 5
m.cur_rom_bank = (m.cur_rom_bank & mbc1_reg_msb_rom_bank_sel_mask) | msb
m.curRomBank = (m.curRomBank & MBC1_REG_MSB_ROM_BANK_SEL_MASK) | msb
}
return mem.WriteBlock()
} else if mbc1_reg_bank_mode_sel.Contains(addr, false) {
} else if MBC1_REG_BANK_MODE_SEL.Contains(addr, false) {
if value == 0x00 {
m.ram_selected = false
m.ramSelected = false
} else if value == 0x01 {
m.ram_selected = true
m.ramSelected = true
}

// TODO: Log something / panic if unexpected value?

return mem.WriteBlock()
} else if mbc1_ram_banks.Contains(addr, false) {
} else if MBC1_RAM_BANKS.Contains(addr, false) {
writeBankAddr(
m.ram,
mbc1_ram_banks,
MBC1_RAM_BANKS,
RAM_BANK_SIZE,
uint16(m.cur_ram_bank),
uint16(m.curRamBank),
addr,
value,
)
Expand Down
90 changes: 45 additions & 45 deletions cart/mbc/mbc5.go
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,62 +7,62 @@ import (
)

var (
mbc5_rom_bank_00 = mem.MemRegion{Start: 0x0000, End: 0x3FFF}
mbc5_rom_banks = mem.MemRegion{Start: 0x4000, End: 0x7FFF}
mbc5_ram_banks = mem.MemRegion{Start: 0xA000, End: 0xBFFF}
MBC5_ROM_BANK_00 = mem.MemRegion{Start: 0x0000, End: 0x3FFF}
MBC5_ROM_BANKS = mem.MemRegion{Start: 0x4000, End: 0x7FFF}
MBC5_RAM_BANKS = mem.MemRegion{Start: 0xA000, End: 0xBFFF}

mbc5_reg_ram_enable = mem.MemRegion{Start: 0x0000, End: 0x1FFF}
mbc5_reg_ram_enable_mask = byte(0xF)
mbc5_reg_ram_enabled = byte(0xA)
mbc5_reg_ram_disabled = byte(0x00)
MBC5_REG_RAM_ENABLE = mem.MemRegion{Start: 0x0000, End: 0x1FFF}
MBC5_REG_RAM_ENABLE_MASK = byte(0xF)
MBC5_REG_RAM_ENABLED = byte(0xA)
MBC5_REG_RAM_DISABLED = byte(0x00)

mbc5_reg_lsb_rom_bank = mem.MemRegion{Start: 0x2000, End: 0x2FFF}
mbc5_reg_lsb_rom_bank_sel_mask = ^uint16(0xFF)
MBC5_REG_LSB_ROM_BANK = mem.MemRegion{Start: 0x2000, End: 0x2FFF}
MBC5_REG_LSB_ROM_BANK_SEL_MASK = ^uint16(0xFF)

mbc5_reg_msb_rom_bank = mem.MemRegion{Start: 0x3000, End: 0x3FFF}
mbc5_reg_msb_rom_bank_sel_mask = ^uint16(0x100)
MBC5_REG_MSB_ROM_BANK = mem.MemRegion{Start: 0x3000, End: 0x3FFF}
MBC5_REG_MSB_ROM_BANK_SEL_MASK = ^uint16(0x100)

mbc5_reg_ram_bank = mem.MemRegion{Start: 0x4000, End: 0x5FFF}
mbc5_reg_ram_bank_sel_mask = byte(0xF)
MBC5_REG_RAM_BANK = mem.MemRegion{Start: 0x4000, End: 0x5FFF}
MBC5_REG_RAM_BANK_SEL_MASK = byte(0xF)
)

type MBC5 struct {
cur_ram_bank uint8
cur_rom_bank uint16
ram []byte
ram_enabled bool
rom []byte
curRamBank uint8
curRomBank uint16
ram []byte
ramEnabled bool
rom []byte
}

func NewMBC5(rom []byte, ram []byte) *MBC5 {
return &MBC5{
cur_ram_bank: 0,
cur_rom_bank: 0,
ram: ram,
ram_enabled: false,
rom: rom,
curRamBank: 0,
curRomBank: 0,
ram: ram,
ramEnabled: false,
rom: rom,
}
}

func (m *MBC5) OnRead(mmu *mem.MMU, addr uint16) mem.MemRead {
if mbc5_rom_bank_00.Contains(addr, false) {
if MBC5_ROM_BANK_00.Contains(addr, false) {
return mem.ReadReplace(m.rom[addr])
} else if mbc5_rom_banks.Contains(addr, false) {
} else if MBC5_ROM_BANKS.Contains(addr, false) {
bankByte := readBankAddr(
m.rom,
mbc5_rom_banks,
MBC5_ROM_BANKS,
ROM_BANK_SIZE,
m.cur_rom_bank,
m.curRomBank,
addr,
)
return mem.ReadReplace(bankByte)
} else if mbc5_ram_banks.Contains(addr, false) {
if m.ram_enabled {
} else if MBC5_RAM_BANKS.Contains(addr, false) {
if m.ramEnabled {
bankByte := readBankAddr(
m.ram,
mbc5_ram_banks,
MBC5_RAM_BANKS,
RAM_BANK_SIZE,
uint16(m.cur_ram_bank),
uint16(m.curRamBank),
addr,
)
return mem.ReadReplace(bankByte)
Expand All @@ -76,32 +76,32 @@ func (m *MBC5) OnRead(mmu *mem.MMU, addr uint16) mem.MemRead {
}

func (m *MBC5) OnWrite(mmu *mem.MMU, addr uint16, value byte) mem.MemWrite {
if mbc5_reg_ram_enable.Contains(addr, false) {
if value&mbc5_reg_ram_enable_mask == mbc5_reg_ram_enabled {
m.ram_enabled = true
} else if value&mbc5_reg_ram_enable_mask == mbc5_reg_ram_disabled {
m.ram_enabled = false
if MBC5_REG_RAM_ENABLE.Contains(addr, false) {
if value&MBC5_REG_RAM_ENABLE_MASK == MBC5_REG_RAM_ENABLED {
m.ramEnabled = true
} else if value&MBC5_REG_RAM_ENABLE_MASK == MBC5_REG_RAM_DISABLED {
m.ramEnabled = false
}

// TODO: Log something / panic if unexpected value?

return mem.WriteBlock()
} else if mbc5_reg_lsb_rom_bank.Contains(addr, false) {
m.cur_rom_bank = (m.cur_rom_bank & mbc5_reg_lsb_rom_bank_sel_mask) | uint16(value)
} else if MBC5_REG_LSB_ROM_BANK.Contains(addr, false) {
m.curRomBank = (m.curRomBank & MBC5_REG_LSB_ROM_BANK_SEL_MASK) | uint16(value)
return mem.WriteBlock()
} else if mbc5_reg_msb_rom_bank.Contains(addr, false) {
} else if MBC5_REG_MSB_ROM_BANK.Contains(addr, false) {
msb := uint16(value) & 0x1 << 8
m.cur_rom_bank = (m.cur_rom_bank & mbc5_reg_msb_rom_bank_sel_mask) | msb
m.curRomBank = (m.curRomBank & MBC5_REG_MSB_ROM_BANK_SEL_MASK) | msb
return mem.WriteBlock()
} else if mbc5_reg_ram_bank.Contains(addr, false) {
m.cur_ram_bank = value & mbc5_reg_ram_bank_sel_mask
} else if MBC5_REG_RAM_BANK.Contains(addr, false) {
m.curRamBank = value & MBC5_REG_RAM_BANK_SEL_MASK
return mem.WriteBlock()
} else if mbc5_ram_banks.Contains(addr, false) {
} else if MBC5_RAM_BANKS.Contains(addr, false) {
writeBankAddr(
m.ram,
mbc5_ram_banks,
MBC5_RAM_BANKS,
RAM_BANK_SIZE,
uint16(m.cur_ram_bank),
uint16(m.curRamBank),
addr,
value,
)
Expand Down
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