Jiffy LOAD: Reduce explicit hold time after last bit pair

Partially reverts commit 8ec7ad5241d97379e7dbaf55f859fec55b7e5d06.

Apparently 11us can be too long for 8MHz devices, see
thierer#3

src/avr/fastloader-ll.S

@@ -437,12 +437,15 @@ jiffy_send:
 
         rcall   jiffy_sendbits  ; 12+4 or 13+5 - [FFD3]
 
-        delay_us 11, -7-RET_OFFSET ; 11 us hold time
+        delay_us 6              ; 6us hold time
 
         ;; Skip sending EOI for LOAD code path
         tst     r20             ; 1
         brne    js_finish       ; 1
 
+        ;; Output EOI marker 11us after the last bitpair
+        delay_us 5, -7-RET_OFFSET
+
         out     _SFR_IO_ADDR(IEC_OUTPUT), r22 ; 1 - output EOI marker [FFDB]
 
         ;; Wait 1us to allow the bus to settle (J1541 needs 4us here)