Simple projects for the RedPitaya board that illustrate the use of standard IPs from Vivado in combination with modules written in Verilog. Tested with Vivado v2019.1, see https://www.xilinx.com/support/download.html. It includes 4 simple projects:
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- Binary Counter Displayed on the LEDs
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- Trigger Counter Displayed on the LEDs
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- Arbitrary Signal on Channel 1 of Fast DAC
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- ADC with nth threshold trigger
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Clone the repositiry
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Create a new project with Vivado.
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Select the device xc7z010clg400-1
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Add the constraint redpitaya.xdc and verilog counter.v files from the repository.
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Create a new Block Design according to the following instructions to creat a block diagram similar to Fig. 1.Binary_Counter.
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Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options.
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Add Module counter.v from the menu.
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Add a Binary Counter from thr Add IP menu.
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Add a port called led_o with components from 7 down to 0.
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From the menu click on Validate Design
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In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper'
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Proceed to run Synthesis, Implementation and Bitstream Generation
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Find the bitstream file (you may use the command 'find . -name *bit')
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Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit)
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Connect to the RedPitaya (ssh root@rp-ip)
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Program the FPGA with the command cat file_name.bit > /dev/xdevcfg
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The 8-bit LEDs will display a binary incremental counter at a rate of 1Hz
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You may change the clock rate by editing the verilog counter.v code.
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Reboot the RedPitaya board or cat fpga_0.94.bit > /dev/xdevcfg to reinstall the official bitstream on the Zynq FPGA.
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Clone the repositiry
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Create a new project with Vivado (tested with Vivado v2019.1) see https://www.xilinx.com/support/download.html
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Select the device xc7z010clg400-1
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Add the constraint redpitaya.xdc and verilog trigger.v files from the repository.
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Create a new Block Design according to the block diagram shown in Fig. 2.Trigger_Counter.png by following the following steps.
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Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options.
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Add the IP called AXI GPIO. Enable Dual Channel and set GPIO 2 to All Inputs with a width of 14 as shown in Fig. 2.AXI_GPIO.png.
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Run Connection Automation with all options selected. Delete the gpio-RTL_0 and gpio-RTL_1 ports.
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From the menu Add Module add trigger.
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From the Add IP menu add Utility Buffer and rigth-click on the plus sign to display the differential IBUF_DS_P and IBUF_DS_N inputs.
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From the Create Port menu add the 3 input ports and the led_o output shown in Fig. 2.Trigger_Counter.png. and make the wire connections shown.
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Note that the base address for the AXI_GPIO is 0x4120_0000, as shown in Fig. 2.Address_Editor.png. We will use this number to communicate to the PL from the PS.
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From the menu click on Validate Design
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In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper'
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Proceed to run Synthesis, Implementation and Bitstream Generation
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Find the bitstream file generated (it is the file with *bit' termination in the ProjectName.runs/impl_1 folder)
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Transfer the bitstream file to the Red Pitaya (you may use *sftp root@rp-ip and the put command line)
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Connect to the RedPitaya (ssh root@rp-ip)
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Program the FPGA with the command cat file_name.bit > /dev/xdevcfg
Now we read the baseline of the ADC-a by using the command line on the RedPitaya using the base address of the AXI_GPIO bus
monitor 0x41200008
In my case I get 0x00002067
Next you can set the treshold a few adc counts from the baseline voltage, i.e.,
monitor 0x41200000 0x2060
You should see the LEDs display in binary the number of trigger signals due to small fluctuations of the baseline.
If you have a signal generator you can set the treshold accodingly.
You can add hysteresis to get more reliable trigger counts.
- Reboot the RedPitaya board or cat fpga_0.94.bit > /dev/xdevcfg to reinstall the official bitstream on the Zynq FPGA.
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Clone the repositiry
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Create a new project with Vivado (tested with Vivado v2019.1) see https://www.xilinx.com/support/download.html
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Select the device xc7z010clg400-1
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Add the constraint redpitaya.xdc and verilog dual_port_ram_dac.v files from the repository.
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Create a new Block Design according to the block diagram shown in Fig. 3.DAC-Arbitrary-Signal-Generator.png by following the following steps.
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Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options.
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Add the IP called AXI GPIO. Set it as shown in Fig. 3.GPIO_0.png.
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Run Connection Automation with all options selected. Delete the gpio-RTL_0 and gpio-RTL_1 ports.
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From the menu Add Module add dual_port_ram_dac.
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From the Add IP menu add Utility Buffer and rigth-click on the plus sign to display the differential IBUF_DS_P and IBUF_DS_N inputs.
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From the Create Port menu add the 3 input ports and the led_o output shown in Fig. 2.Trigger_Counter.png. and make the wire connections shown.
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Note that the base address for the AXI_GPIO is 0x4120_0000. We will use this number to communicate to the PL from the PS.
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From the menu click on Validate Design
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In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper'
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Proceed to run Synthesis, Implementation and Bitstream Generation
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Find the bitstream file generated (it is the file with *bit' termination in the ProjectName.runs/impl_1 folder)
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Transfer the bitstream file to the Red Pitaya (you may use *sftp root@rp-ip and the put command line)
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Connect to the RedPitaya (ssh root@rp-ip)
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Program the FPGA with the command cat file_name.bit > /dev/xdevcfg or use the bit file provided: cat DAC-ASG.bit > /dev/xdevcfg
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Use the Jupyter-Notebook called DAC-ASG.ipynb provided to load an arbitrary waveform and to send it to channel 1 of the fast DAC.
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To see the signal you need an oscilloscope, or, alternatively, check the next project which generates an arbitrary signal on channel 1 of the fast DAC and acquires it with channel 1 of the fast ADC.
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Reboot the RedPitaya board or cat fpga_0.94.bit > /dev/xdevcfg to reinstall the official bitstream on the Zynq FPGA.
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Clone the repositiry
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Create a new project with Vivado (tested with Vivado v2019.1) see https://www.xilinx.com/support/download.html
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Select the device xc7z010clg400-1
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Add the constraint redpitaya.xdc and the required verilog files from the repository.
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Compile and program the FPGA with the command cat file_name.bit > /dev/xdevcfg or use the bit file provided: cat 4.DAC-ADC.bit > /dev/xdevcfg
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Use the Jupyter-Notebook called 4.DAC-ADC.ipynb provided.
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Reboot the RedPitaya board or cat fpga_0.94.bit > /dev/xdevcfg to reinstall the official bitstream on the Zynq FPGA.