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Add more options for VexRiscv generation. #15

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@tcal-x tcal-x commented Oct 7, 2021

No changes to default behavior or to generation
of existing variants.

I tested by regenerating all VexRiscv variant Verilogs,
to ensure that I did not accidentally introduce any behavior
changes. There were no changes other than the embedded hashes.

Signed-off-by: Tim Callahan [email protected]

No changes to default behavior or to generation
of existing variants.

I tested by regenerating all VexRiscv variant Verilogs,
to ensure that I did not accidentally introduce any behavior
changes.  There were no changes other than the embedded hashes.

Signed-off-by: Tim Callahan <[email protected]>
for (idx <- 0 until csrCount) {

val cycleCounter = Reg(UInt(32 bits))
val enable = Reg(UInt(32 bits)) // only the LSB is used
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val enable = Reg(Bool()) init(False)
...
csrService.w( 0xB04 + idx * 2 + 1, enable)

should be fine, i guess :)

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It seems the extra 31 registers did get trimmed away since they were not readable and not used, but I have made the change to make the enable explicitly Bool.

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Hoooo yes, you are right, haven't seen it

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