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Ensoniq DOC
This register contains the status of the DOC intermpt request (IRQ) pin and the number of the oscillator that generated the interrupt, if any, When an oscillator reaches the end of a wavetable and the enable interrupt (EI) bit for that oscillator has previously been set, the IRQ line and bit 7 of the Oscillator Interrupt register are then set, and the register number is entered in bits 1 through 5 of the Oscillator Interrupt register. Figure 5-4 shows the format of the Oscillator Interrupt register. Table 5-3 gives a description of each of the bits.
| Bit | Description |
|---|---|
| 7 | Interrupt occurred |
| 6 | Reserved |
| 5-1 | Oscillator number |
| 0 | Reserved |
The Oscillator Enable register controls the number of oscillators that are operating at a particular time, To enable 1 or more oscillators, multiply the desired quantity of oscillators (up to 32) by 2 and enter the number in this register at $E1. You may enter any number from 2 to 64, which will enable the corresponding oscillators in sequential order. (Low-numbered oscillators cannot be skipped in order to enable a higher-numbered one.) A minimum of 1 oscillator is always enabled, which is also the reset default.
The A/D Converter register contains the output value of the successive-approximation analog-to-digital converter. An analog-input signal can be sampled at pin 1 of the 7-pin molex connector (J25). The result of the conversion resides in the A/D Converter register at the completion of lhe conversion. Reading this register at $E2 initiates the 31-microsecond conversion process. If this register is read before the end of the conversion process, the value will be lost and a new conversion will begin.
Table 5-4 contains the addresses for the registers dedicated to the individual oscillators.
Each Oscillator Control register controls all functions of each oscillator, including
- which of eight optional external analog multiplexer channels an oscillator will use
- whether or not an oscillator may generate an interrupt
- the oscillator's mode of operation
| Register | Address |
|---|---|
| Frequency Low | $00-$1f |
| Frequency High | $20-$3f |
| Volume | $40-$5f |
| Data | $60-$7f |
| Wavetable Pointer | $80-$9f |
| Control | $a0-$bf |
| Wavetable Size | $c0-$df |
- Oscillators $1e and $1f are reserved for system use. Use of these oscillators by the user may result in a system crash.
The oscillator may function in one of several modes:
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Free Run mode: The oscillator begins at the beginning of the wavetable and repeats the same wavetable. The oscillator will halt when the halt bit is set or when a 0 is encountered in the table data.
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One Shot mode: The oscillator begins at the beginning of the wavetable. stepping through it only once, and stopping at the end of the table.
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Sync mode: You enable Sync mode by selecting even/odd pairs of oscillators (a lower even-numbered oscillator paired with an adjacent higher-numbered oscillator). When the even-numbered oscillator begins its wavetable, the odd-mate oscillator will synchronize and begin its wavetable simultaneously.
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Swap mode: Uses even/odd pairs of oscillators (a lower even-numbered oscillator paired with an adjacent higher odd-numbered oscillator). The enabled oscillator pair runs in One Shot mode. When it reaches the end of its wavetable, it resets its accumulator to 0, sets its halt bit, and clears the halt bit of its mate.
Figure 5-5 shows the format of this register. Table 5-5 gives a description of each bit.
| Bit | Description |
|---|---|
| 7-4 | Channel address |
| 3 | Oscillator interrupt enable |
| 2-1 | Oscillator mode |
| 0 | Halted oscillator |
The Oscillator Data registers are read-only registers and contain the last byte read by an oscillator from the wavetable.
The Volume registers contain an oscillator's volume value. The current wavetable data byte is multiplied by the 8-bit volume value to obtain the oscillator final output level.
The Frequency High registers and Frequency Low registers are concatenated to create a 16- bit value for each oscillator. This frequency value determines the speed at which the wavetable is read from memory. This speed indirectly- determines the frequency of the output signal at the speaker. The relationship between output signal frequency, wavetable scan rate, and the Frequency High and Frequency Low register values is
Output frequency = (SR * FHL) / (2 ^ (17+RES))
where
- the scan rate SR = 894.886KHZ / (OSC + 2)
- RES is the resolution value in the Wavetable register.
- FHL is the 16-bit frequency value concatenated from the Frequency High and Frequency Low registers
- OSC is the number of enabled oscillators.
n.b.:
- OSC+2 since 2 cycles are needed for RAM refresh
- NTSC clock is 14.31818 Mhz. Dividing by 16 gives 894.88625 Khz. This is slightly under-clocked (it's designed for 1Mhz).
- With 32 oscillators enabled (standard for toolsets), the playback rate is 26.3khz
- With 18 oscillators enabled, the playback rate is 44.7 Khz
- The IIgs has a 26khz low pass filter.