ScottoModules STM32F072CBT6 Rework

[Cipulot]

Description

This PR aims to address issues found in the original template and implement improved EE practices.

Although the previous project was functional and tested with other boards by @joe-scotto , it is best practice to encourage proper EE considerations for the schematics and PCB layout due to the nature of the project.

List of changes

Repository

• Fixed a typo in the general repository README (publically --> publicly)
• Update .gitignore to ignore .DS_Store files too

Schematic

• Swap of symbols and PCB footprints from ScottoKeebs specific ones to standard KiCad library for integrity
• Swap of the specific USB-C symbol used for a standard one to address missing pin A8 and B8 DRC error
• Moved away from the use of Global Ports in favor of Net Labels, given the one-sheet nature of the template
• Specifically separated VDD nets to highlight the proper decoupling capacitors pairing pins better (of course they all retrieve back to +3.3V)
• Implemented datasheet-oriented decoupling capacitor values
• Addition of MPN for all components used
• Addition of Power Flags
• Separated the Data Lines between the USB-C side and MCU side, this is to achieve proper ESD isolation in the PCB layout, where the pins were previously shorted
• ESD VCC is now tied to VBUS or proper VBUS ESD suppression
• Added a small note on DFU procedure steps

PCB Layout

• Removal of the 2 groups
• Added a PCB edge for demonstration purposes
• Added a GND fill area on the top and bottom area for demonstration purposes (the electrical properties differ from the standard ones from KiCad to showcase a realistic usage)
• Manually swapped the .wrl 3D models extensions to .step when a model is available to allow users to have exported PCBs step models with components (it's KiCad default to use .wrl even tho the exporter cannot convert .wrl component models to .step to have them in the final model)
• Reroute the 2 blocks so that they follow good design practices and reflect the changes applied in the schematic:

[joe-scotto]

Thank you very much for this! I ended up manually implementing a lot of these changes on the stm-32 branch. I will be doing a follow up video to cover these changes but this will replace the current version of ScottoModules soon. The modules are still the same in that you only need to run D+, D-, BOOT0, and 3.3V. I'll note that tolerances are very close for the modules in order to make them work but they pass DRC.

Changes

Repository

• Update .gitignore to ignore .DS_Store files too
• Fixed a typo in the general repository README (publically --> publicly)

Schematic

• Swap of symbols and PCB footprints from ScottoKeebs specific ones to standard KiCad library for integrity
  • Omitted as to keep in line with my videos to use my library. Might reinvestigate one day.
• Swap of the specific USB-C symbol used for a standard one to address missing pin A8 and B8 DRC error
  • I do not get a DRC error with this footprint on Kicad 8.
• Specifically separated VDD nets to highlight the proper decoupling capacitors pairing pins better (of course they all retrieve back to +3.3V)
• Implemented datasheet-oriented decoupling capacitor values
• Addition of MPN for all components used
• Addition of Power Flags
• Separated the Data Lines between the USB-C side and MCU side, this is to achieve proper ESD isolation in the PCB layout, where the pins were previously shorted
• ESD VCC is now tied to VBUS or proper VBUS ESD suppression
• Added a small note on DFU procedure steps
• Moved away from the use of Global Ports in favor of Net Labels, given the one-sheet nature of the template

PCB Layout

• Removal of the 2 groups
  • Omitted because it would defeat the overall concept behind ScottoModules
• Manually swapped the .wrl 3D models extensions to .step when a model is available to allow users to have exported PCBs step models with components (it's KiCad default to use .wrl even tho the exporter cannot convert .wrl component models to .step to have them in the final model)
  • Eventually I will look into this since the footprints are within my personal library.
• Added a PCB edge for demonstration purposes.
• Added a GND fill on inner layers for demonstration purposes.
• Added simple grid switch layout to demonstrate placement.
• Reroute the 2 blocks so that they follow good design practices and reflect the changes applied in the schematic:

Other

• Default to 4 layer PCB for a more solid GND layer at the expense of production cost. Should also be better for EMI if there is any.
  • 2 layer should still work but 4 just seemed like a better standard to follow.
• Added Other section to schematic for common items like mounting holes and a pre-defined area for the matrix.
• Rename Reset to Bootloader button.
• Route bootloader button better in order to avoid having traces run behind it other than what's needed for it to function.
• VBUS -> ESD -> Fuse -> Power Converter