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Fix various spelling mistakes and typos as found using codespell #96

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Fix various spelling mistakes and typos as found using codespell #96

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677dc96
Fix various spelling mistakes and typos as found using codespell
ColinIanKing Aug 2, 2023
37fcb3c
Fix even spelling mistakes found using the spell tool
ColinIanKing Sep 28, 2023
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4 changes: 2 additions & 2 deletions ADL/events/alderlake_goldencove_core.json
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Expand Up @@ -3132,7 +3132,7 @@
"UMask": "0x08",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
"Counter": "0",
"PEBScounters": "0",
"SampleAfterValue": "10000003",
Expand Down Expand Up @@ -7016,4 +7016,4 @@
"Speculative": "1"
}
]
}
}
6 changes: 3 additions & 3 deletions Atom_TMA.csv
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Expand Up @@ -32,7 +32,7 @@ BE_aux,,,Reorder_Buffer,,TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS,,,Slots,Counts
BE_aux,,,Store_Buffer,,TOPDOWN_BE_BOUND.STORE_BUFFER / SLOTS,,,Slots,Counts the number of issue slots that were not consumed by the backend due to store buffers stalls.,,>0.10
BE_aux,,,Alloc_Restriction,,TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS,,,Slots,Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.,,>0.10
BE_aux,,,Serialization,,TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS,,,Slots,"Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",,>0.10
RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,UOPS_RETIRED.ANY / SLOTS ,,Slots,Counts the numer of issue slots that result in retirement slots. ,,>0.75
RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,UOPS_RETIRED.ANY / SLOTS ,,Slots,Counts the number of issue slots that result in retirement slots. ,,>0.75
RET,,Base,,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS ) / SLOTS,,,Slots,Counts the number of uops that are not from the microsequencer. ,,>0.60
RET,,,FPDIV_uops,,UOPS_RETIRED.FPDIV / SLOTS,UOPS_RETIRED.FPDIV / SLOTS,,Slots,Counts the number of floating point divide operations per uop.,,>0.20
RET,,,Other_Ret,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV ) / SLOTS,,,Slots,Counts the number of uops retired excluding ms and fp div uops.,,>0.30
Expand All @@ -47,8 +47,8 @@ Info.Core,UPI,,,,UOPS_RETIRED.ALL / INST_RETIRED.ANY,UOPS_RETIRED.ANY / INST_RET
Info.L1_Bound,Store_Fwd_Blocks,,,,100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS,100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a store forward or unknown store address block,,
Info.L1_Bound,Address_Alias_Blocks,,,,100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS,100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a address aliasing block,,
Info.L1_Bound,Load_Splits,,,,100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS,100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads that are splits,,
Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurance rate), ,
Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurance rate), ,
Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurrence rate), ,
Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurrence rate), ,
Info.Inst_Mix,IpLoad,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS,,,Instructions per Load, ,
Info.Inst_Mix,IpStore,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES,,,Instructions per Store, ,
Info.Inst_Mix,IpMispredict,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,,,Instructions per retired Branch Misprediction, ,
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64 changes: 32 additions & 32 deletions BDW-DE/events/broadwellde_uncore.json
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64 changes: 32 additions & 32 deletions BDX/events/broadwellx_uncore.json
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6 changes: 3 additions & 3 deletions CLX/events/cascadelakex_core.json
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Expand Up @@ -1020,7 +1020,7 @@
"UMask": "0x20",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
Expand Down Expand Up @@ -3060,7 +3060,7 @@
"UMask": "0x10",
"EventName": "ITLB_MISSES.WALK_PENDING",
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
Expand Down Expand Up @@ -56240,4 +56240,4 @@
"Deprecated": "0"
}
]
}
}
16 changes: 8 additions & 8 deletions CLX/events/cascadelakex_uncore_experimental.json
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Expand Up @@ -4408,7 +4408,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"BriefDescription": "Coherent Ops; PCIRdCur",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand All @@ -4426,7 +4426,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"BriefDescription": "Coherent Ops; CRd",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand All @@ -4444,7 +4444,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"BriefDescription": "Coherent Ops; DRd",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand All @@ -4462,7 +4462,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"BriefDescription": "Coherent Ops; PCIDCAHin5t",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand All @@ -4480,7 +4480,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"BriefDescription": "Coherent Ops; WbMtoI",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand All @@ -4498,7 +4498,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"BriefDescription": "Coherent Ops; CLFlush",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand Down Expand Up @@ -5182,7 +5182,7 @@
"UMaskExt": "0x00",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"BriefDescription": "Inbound Transaction Count; Writes",
"PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
"PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
"Counter": "0,1",
"MSRValue": "0x00",
"ELLC": "0",
Expand Down Expand Up @@ -56438,4 +56438,4 @@
"FILTER_VALUE": "0"
}
]
}
}
6 changes: 3 additions & 3 deletions E-core_TMA_Metrics.csv
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Expand Up @@ -46,7 +46,7 @@ BE_aux,,,Register,,TOPDOWN_BE_BOUND.REGISTER / SLOTS,,Slots,Counts the number of
BE_aux,,,Reorder_Buffer,,TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS,,Slots,Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).,,>0.10
BE_aux,,,Alloc_Restriction,,TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS,,Slots,Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.,,>0.10
BE_aux,,,Serialization,,TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS,,Slots,"Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",,>0.10
RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,,Slots,Counts the numer of issue slots that result in retirement slots. ,,>0.75
RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,,Slots,Counts the number of issue slots that result in retirement slots. ,,>0.75
RET,,Base,,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS ) / SLOTS,,Slots,Counts the number of uops that are not from the microsequencer. ,,>0.60
RET,,,FPDIV_uops,,UOPS_RETIRED.FPDIV / SLOTS,,Slots,Counts the number of floating point divide operations per uop.,,>0.20
RET,,,Other_Ret,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV ) / SLOTS,,Slots,Counts the number of uops retired excluding ms and fp div uops.,,>0.30
Expand All @@ -61,8 +61,8 @@ Info.Core,UPI,,,,UOPS_RETIRED.ALL / INST_RETIRED.ANY,,,Uops Per Instruction, ,
Info.L1_Bound,Store_Fwd_Blocks,,,,100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a store forward or unknown store address block,,
Info.L1_Bound,Address_Alias_Blocks,,,,100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a address aliasing block,,
Info.L1_Bound,Load_Splits,,,,100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads that are splits,,
Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurance rate), ,
Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurance rate), ,
Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurrence rate), ,
Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurrence rate), ,
Info.Inst_Mix,IpLoad,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS,,,Instructions per Load, ,
Info.Inst_Mix,IpStore,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES,,,Instructions per Store, ,
Info.Inst_Mix,IpMispredict,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,,,Instructions per retired Branch Misprediction, ,
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4 changes: 2 additions & 2 deletions HSW/events/haswell_core.json
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Expand Up @@ -5831,7 +5831,7 @@
"UMask": "0x02",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
Expand Down Expand Up @@ -8656,4 +8656,4 @@
"Deprecated": "0"
}
]
}
}
4 changes: 2 additions & 2 deletions HSX/events/haswellx_core.json
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Expand Up @@ -6084,7 +6084,7 @@
"UMask": "0x02",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
Expand Down Expand Up @@ -9272,4 +9272,4 @@
"Deprecated": "0"
}
]
}
}
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