Merge pull request #179 from edwarddavidbaker/sync-platforms

GNR, ICX, SNR: Release event updates
intel · May 13, 2024 · ffc9da6 · ffc9da6
2 parents 1424ebf + 9debd87
commit ffc9da6
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Showing 10 changed files with 22,189 additions and 473 deletions.
diff --git a/GNR/events/graniterapids_core.json b/GNR/events/graniterapids_core.json
diff --git a/GNR/events/graniterapids_uncore.json b/GNR/events/graniterapids_uncore.json
diff --git a/GNR/events/graniterapids_uncore_experimental.json b/GNR/events/graniterapids_uncore_experimental.json
diff --git a/ICX/events/icelakex_core.json b/ICX/events/icelakex_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.25",
-    "DatePublished": "04/03/2024",
-    "Version": "1.25",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.26",
+    "DatePublished": "04/24/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [

diff --git a/ICX/events/icelakex_uncore.json b/ICX/events/icelakex_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.25",
-    "DatePublished": "04/03/2024",
-    "Version": "1.25",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.26",
+    "DatePublished": "04/24/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [

diff --git a/ICX/events/icelakex_uncore_experimental.json b/ICX/events/icelakex_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.25",
-    "DatePublished": "04/03/2024",
-    "Version": "1.25",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.26",
+    "DatePublished": "04/24/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [
@@ -3049,60 +3049,6 @@
       "FILTER_VALUE": "0",
       "CounterType": "PGMABLE"
     },
-    {
-      "Unit": "CHA",
-      "EventCode": "0x42",
-      "UMask": "0x00",
-      "PortMask": "0x00",
-      "FCMask": "0x00",
-      "UMaskExt": "0x4000000",
-      "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
-      "BriefDescription": "Pipe Rejects",
-      "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
-      "Counter": "0,1,2,3",
-      "ELLC": "0",
-      "Filter": "na",
-      "ExtSel": "0",
-      "Deprecated": "0",
-      "FILTER_VALUE": "0",
-      "CounterType": "PGMABLE"
-    },
-    {
-      "Unit": "CHA",
-      "EventCode": "0x42",
-      "UMask": "0x00",
-      "PortMask": "0x00",
-      "FCMask": "0x00",
-      "UMaskExt": "0x8000000",
-      "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
-      "BriefDescription": "Pipe Rejects",
-      "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
-      "Counter": "0,1,2,3",
-      "ELLC": "0",
-      "Filter": "na",
-      "ExtSel": "0",
-      "Deprecated": "0",
-      "FILTER_VALUE": "0",
-      "CounterType": "PGMABLE"
-    },
-    {
-      "Unit": "CHA",
-      "EventCode": "0x42",
-      "UMask": "0x00",
-      "PortMask": "0x00",
-      "FCMask": "0x00",
-      "UMaskExt": "0x10000000",
-      "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
-      "BriefDescription": "Pipe Rejects",
-      "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
-      "Counter": "0,1,2,3",
-      "ELLC": "0",
-      "Filter": "na",
-      "ExtSel": "0",
-      "Deprecated": "0",
-      "FILTER_VALUE": "0",
-      "CounterType": "PGMABLE"
-    },
     {
       "Unit": "CHA",
       "EventCode": "0x58",

diff --git a/SNR/events/snowridgex_core.json b/SNR/events/snowridgex_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.22",
-    "DatePublished": "03/08/2024",
-    "Version": "1.22",
+    "Info": "Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.23",
+    "DatePublished": "04/24/2024",
+    "Version": "1.23",
     "Legend": ""
   },
   "Events": [

diff --git a/SNR/events/snowridgex_uncore.json b/SNR/events/snowridgex_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.22",
-    "DatePublished": "03/08/2024",
-    "Version": "1.22",
+    "Info": "Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.23",
+    "DatePublished": "04/24/2024",
+    "Version": "1.23",
     "Legend": ""
   },
   "Events": [

diff --git a/SNR/events/snowridgex_uncore_experimental.json b/SNR/events/snowridgex_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.22",
-    "DatePublished": "03/08/2024",
-    "Version": "1.22",
+    "Info": "Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.23",
+    "DatePublished": "04/24/2024",
+    "Version": "1.23",
     "Legend": ""
   },
   "Events": [
@@ -2059,60 +2059,6 @@
       "FILTER_VALUE": "0",
       "CounterType": "PGMABLE"
     },
-    {
-      "Unit": "CHA",
-      "EventCode": "0x42",
-      "UMask": "0x00",
-      "PortMask": "0x00",
-      "FCMask": "0x00",
-      "UMaskExt": "0x4000000",
-      "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
-      "BriefDescription": "Pipe Rejects",
-      "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
-      "Counter": "0,1,2,3",
-      "ELLC": "0",
-      "Filter": "na",
-      "ExtSel": "0",
-      "Deprecated": "0",
-      "FILTER_VALUE": "0",
-      "CounterType": "PGMABLE"
-    },
-    {
-      "Unit": "CHA",
-      "EventCode": "0x42",
-      "UMask": "0x00",
-      "PortMask": "0x00",
-      "FCMask": "0x00",
-      "UMaskExt": "0x8000000",
-      "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
-      "BriefDescription": "Pipe Rejects",
-      "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
-      "Counter": "0,1,2,3",
-      "ELLC": "0",
-      "Filter": "na",
-      "ExtSel": "0",
-      "Deprecated": "0",
-      "FILTER_VALUE": "0",
-      "CounterType": "PGMABLE"
-    },
-    {
-      "Unit": "CHA",
-      "EventCode": "0x42",
-      "UMask": "0x00",
-      "PortMask": "0x00",
-      "FCMask": "0x00",
-      "UMaskExt": "0x10000000",
-      "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
-      "BriefDescription": "Pipe Rejects",
-      "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
-      "Counter": "0,1,2,3",
-      "ELLC": "0",
-      "Filter": "na",
-      "ExtSel": "0",
-      "Deprecated": "0",
-      "FILTER_VALUE": "0",
-      "CounterType": "PGMABLE"
-    },
     {
       "Unit": "CHA",
       "EventCode": "0x58",

diff --git a/mapfile.csv b/mapfile.csv
@@ -109,9 +109,9 @@ GenuineIntel-6-7E,V1.22,/ICL/events/icelake_uncore_experimental.json,uncore expe
 GenuineIntel-6-A7,V1.03,/RKL/events/rocketlake_core.json,core,,,
 GenuineIntel-6-A7,V1.03,/RKL/events/rocketlake_uncore.json,uncore,,,
 GenuineIntel-6-A7,V1.03,/RKL/events/rocketlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-86,V1.22,/SNR/events/snowridgex_core.json,core,,,
-GenuineIntel-6-86,V1.22,/SNR/events/snowridgex_uncore.json,uncore,,,
-GenuineIntel-6-86,V1.22,/SNR/events/snowridgex_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-86,V1.23,/SNR/events/snowridgex_core.json,core,,,
+GenuineIntel-6-86,V1.23,/SNR/events/snowridgex_uncore.json,uncore,,,
+GenuineIntel-6-86,V1.23,/SNR/events/snowridgex_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-8C,V1.16,/TGL/events/tigerlake_core.json,core,,,
 GenuineIntel-6-8D,V1.16,/TGL/events/tigerlake_core.json,core,,,
 GenuineIntel-6-8C,V1.16,/TGL/events/tigerlake_uncore.json,uncore,,,
@@ -124,12 +124,12 @@ GenuineIntel-6-8F,V1.22,/SPR/events/sapphirerapids_uncore_experimental.json,unco
 GenuineIntel-6-CF,V1.08,/EMR/events/emeraldrapids_core.json,core,,,
 GenuineIntel-6-CF,V1.08,/EMR/events/emeraldrapids_uncore.json,uncore,,,
 GenuineIntel-6-CF,V1.08,/EMR/events/emeraldrapids_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-6A,V1.25,/ICX/events/icelakex_core.json,core,,,
-GenuineIntel-6-6A,V1.25,/ICX/events/icelakex_uncore.json,uncore,,,
-GenuineIntel-6-6A,V1.25,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-6C,V1.25,/ICX/events/icelakex_core.json,core,,,
-GenuineIntel-6-6C,V1.25,/ICX/events/icelakex_uncore.json,uncore,,,
-GenuineIntel-6-6C,V1.25,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-6A,V1.26,/ICX/events/icelakex_core.json,core,,,
+GenuineIntel-6-6A,V1.26,/ICX/events/icelakex_uncore.json,uncore,,,
+GenuineIntel-6-6A,V1.26,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-6C,V1.26,/ICX/events/icelakex_core.json,core,,,
+GenuineIntel-6-6C,V1.26,/ICX/events/icelakex_uncore.json,uncore,,,
+GenuineIntel-6-6C,V1.26,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-96,V1.05,/EHL/events/elkhartlake_core.json,core,,,
 GenuineIntel-6-9C,V1.05,/EHL/events/elkhartlake_core.json,core,,,
 GenuineIntel-6-97,V1.26,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
@@ -163,8 +163,12 @@ GenuineIntel-6-AC,V1.09,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x
 GenuineIntel-6-AC,V1.09,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core
 GenuineIntel-6-AC,V1.09,/MTL/events/meteorlake_uncore.json,uncore,,,
 GenuineIntel-6-AC,V1.09,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-AD,V1.01,/GNR/events/graniterapids_core.json,core,,,
-GenuineIntel-6-AE,V1.01,/GNR/events/graniterapids_core.json,core,,,
+GenuineIntel-6-AD,V1.02,/GNR/events/graniterapids_core.json,core,,,
+GenuineIntel-6-AD,V1.02,/GNR/events/graniterapids_uncore.json,uncore,,,
+GenuineIntel-6-AD,V1.02,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-AE,V1.02,/GNR/events/graniterapids_core.json,core,,,
+GenuineIntel-6-AE,V1.02,/GNR/events/graniterapids_uncore.json,uncore,,,
+GenuineIntel-6-AE,V1.02,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-AF,V1.03,/SRF/events/sierraforest_core.json,core,,,
 GenuineIntel-6-AF,V1.03,/SRF/events/sierraforest_uncore.json,uncore,,,
 GenuineIntel-6-AF,V1.03,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,,