transactions and diffs (#44)

intel · Jun 22, 2023 · 75f8a93 · 75f8a93
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diff --git a/README.md b/README.md
@@ -1,4 +1,4 @@
-# PerfSpect &middot; [![Build](https://github.com/intel/PerfSpect/actions/workflows/build.yml/badge.svg)](https://github.com/intel/PerfSpect/actions/workflows/build.yml)[![License](https://img.shields.io/badge/License-BSD--3-blue)](https://github.com/intel/PerfSpect/blob/master/LICENSE)
+# PerfSpect &middot; [![Build](https://github.com/intel/PerfSpect/actions/workflows/build.yml/badge.svg)](https://github.com/intel/PerfSpect/actions/workflows/build.yml)[![CodeQL](https://github.com/intel/PerfSpect/actions/workflows/codeql.yml/badge.svg)](https://github.com/intel/PerfSpect/actions/workflows/codeql.yml)[![License](https://img.shields.io/badge/License-BSD--3-blue)](https://github.com/intel/PerfSpect/blob/master/LICENSE)
 
 [Quick Start](#quick-start-requires-perf-installed) | [Output](#output) | [Requirements](#requirements) | [Build from source](#build-from-source)
 
@@ -79,4 +79,4 @@ Requires recent python. On successful build, binaries will be created in `dist`
 ```
 pip3 install -r requirements.txt
 make
-```
+```
diff --git a/_version.txt b/_version.txt
@@ -1 +1 @@
-1.3.1
+1.3.2
diff --git a/events/metric_bdx.json b/events/metric_bdx.json
@@ -14,67 +14,97 @@
     },
     {
         "name": "metric_CPI",
-        "expression": "[cpu-cycles] / [instructions]"
+        "name-txn": "metric_cycles per txn",
+        "expression": "[cpu-cycles] / [instructions]",
+        "expression-txn": "[cpu-cycles] / [TXN]"
     },
     {
         "name": "metric_kernel_CPI",
+        "name-txn": "metric_kernel_cycles per txn",
         "expression": "[cpu-cycles:k] / [instructions:k]",
+        "expression-txn": "[cpu-cycles:k] / [TXN]",
         "origin": "perfspect"
     },
     {
         "name": "metric_locks retired per instr",
+        "name-txn": "metric_locks retired per txn",
         "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]",
+        "expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]", 
         "origin": "perfmon website"
     },
     {
         "name": "metric_L1D MPI (includes data+rfo w/ prefetches)",
-        "expression": "[L1D.REPLACEMENT] / [instructions]"
+        "name-txn": "metric_L1D misses per txn (includes data+rfo w/ prefetches)",
+        "expression": "[L1D.REPLACEMENT] / [instructions]",
+        "expression-txn": "[L1D.REPLACEMENT] / [TXN]"
     },
     {
         "name": "metric_L1D demand data read hits per instr",
-        "expression": "[MEM_LOAD_UOPS_RETIRED.L1_HIT] / [instructions]"
+        "name-txn": "metric_L1D demand data read hits per txn",
+        "expression": "[MEM_LOAD_UOPS_RETIRED.L1_HIT] / [instructions]",
+        "expression-txn": "[MEM_LOAD_UOPS_RETIRED.L1_HIT] / [TXN]"
     },
     {
         "name": "metric_L1-I code read misses (w/ prefetches) per instr",
-        "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]"
+        "name-txn": "metric_L1-I code read misses (w/ prefetches) per txn",
+        "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]",
+        "expression-txn": "[L2_RQSTS.ALL_CODE_RD] / [TXN]"
     },
     {
         "name": "metric_L2 demand data read hits per instr",
-        "expression": "[MEM_LOAD_UOPS_RETIRED.L2_HIT] / [instructions]"
+        "name-txn": "metric_L2 demand data read hits per txn",
+        "expression": "[MEM_LOAD_UOPS_RETIRED.L2_HIT] / [instructions]",
+        "expression-txn": "[MEM_LOAD_UOPS_RETIRED.L2_HIT] / [txn]"
     },
     {
         "name": "metric_L2 MPI (includes code+data+rfo w/ prefetches)",
-        "expression": "[L2_LINES_IN.ALL] / [instructions]"
+        "name-txn": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)",
+        "expression": "[L2_LINES_IN.ALL] / [instructions]",
+        "expression-txn": "[L2_LINES_IN.ALL] / [TXN]"
     },
     {
         "name": "metric_L2 demand data read MPI",
-        "expression": "[MEM_LOAD_UOPS_RETIRED.L2_MISS] / [instructions]"
+        "name-txn": "metric_L2 demand data read misses per txn",
+        "expression": "[MEM_LOAD_UOPS_RETIRED.L2_MISS] / [instructions]",
+        "expression-txn": "[MEM_LOAD_UOPS_RETIRED.L2_MISS] / [TXN]"
     },
     {
         "name": "metric_L2 demand code MPI",
-        "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]"
+        "name-txn": "metric_L2 demand code misses per txn",
+        "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]",
+        "expression-txn": "[L2_RQSTS.CODE_RD_MISS] / [TXN]"
     },
     {
         "name": "metric_LLC MPI",
+        "name-txn": "metric_LLC misses per txn (includes code+data+rfo w/ prefetches)",
         "expression": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x180] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x181] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x182] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x190] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x191] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x192] - [UNC_C_TOR_INSERTS.MISS_OPCODE.tid.0x180]) / [instructions]",
+        "expression-txn": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x180] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x181] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x182] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x190] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x191] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x192] - [UNC_C_TOR_INSERTS.MISS_OPCODE.tid.0x180]) / [TXN]",
         "origin": "perfspect"
     },
     {
         "name": "metric_LLC code read MPI (demand+prefetch)",
-        "expression": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x181] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x191]) / [instructions]"
+        "name-txn": "metric_LLC code read (demand+prefetch) misses per txn",
+        "expression": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x181] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x191]) / [instructions]",
+        "expression-txn": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x181] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x191]) / [TXN]"
     },
     {
         "name": "metric_LLC data read MPI (demand+prefetch)",
-        "expression": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x182] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x192]) / [instructions]"
+        "name-txn": "metric_LLC data read (demand+prefetch) misses per txn",
+        "expression": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x182] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x192]) / [instructions]",
+        "expression-txn": "([UNC_C_TOR_INSERTS.MISS_OPCODE.0x182] + [UNC_C_TOR_INSERTS.MISS_OPCODE.0x192]) / [TXN]"
     },
     {
         "name": "metric_LLC total HITM (per instr)",
+        "name-txn": "metric_LLC total HITM per txn (excludes LLC prefetches)",
         "expression": "[OCR.ALL_READS.L3_MISS.REMOTE_HITM] / [instructions]",
+        "expression-txn": "[OCR.ALL_READS.L3_MISS.REMOTE_HITM] / [TXN]",
         "origin": "perfspect"
     },
     {
         "name": "metric_LLC total HIT clean line forwards (per instr)",
+        "name-txn": "metric_LLC total HIT clean line forwards per txn (excludes LLC prefetches)",
         "expression": "[OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD] / [instructions]",
+        "expression-txn": "[OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD] / [TXN]",
         "origin": "perfspect"
     },
     {
@@ -99,24 +129,34 @@
     },
     {
         "name": "metric_ITLB MPI",
-        "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]"
+        "name-txn": "metric_ITLB misses per txn",
+        "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]",
+        "expression-txn": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]"
     },
     {
         "name": "metric_ITLB large page MPI",
-        "expression": "[ITLB_MISSES.WALK_COMPLETED_2M_4M] / [instructions]"
+        "name-txn": "metric_ITLB large page misses per txn",
+        "expression": "[ITLB_MISSES.WALK_COMPLETED_2M_4M] / [instructions]",
+        "expression-txn": "[ITLB_MISSES.WALK_COMPLETED_2M_4M] / [TXN]"
     },
     {
         "name": "metric_DTLB load MPI",
-        "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]"
+        "name-txn": "metric_DTLB load misses per txn",
+        "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]",
+        "expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]"
     },
     {
         "name": "metric_DTLB 2MB large page load MPI",
+        "name-txn": "metric_DTLB 2MB large page load misses per txn",
         "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]",
+        "expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]",
         "origin": "perfspect"
     },
     {
         "name": "metric_DTLB store MPI",
-        "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]"
+        "name-txn": "metric_DTLB store misses per txn",
+        "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]",
+        "expression-txn": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]"
     },
     {
         "name": "metric_DTLB load miss latency (in core clks)",
@@ -346,4 +386,4 @@
         "expression": "100 * (([UOPS_RETIRED.RETIRE_SLOTS] / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] )/ (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))",
         "origin": "perfspect"
     }
-]
+]
diff --git a/events/metric_icx.json b/events/metric_icx.json
@@ -14,16 +14,22 @@
     },
     {
         "name": "metric_CPI",
-        "expression": "[cpu-cycles] / [instructions]"
+		"name-txn": "metric_cycles per txn",
+        "expression": "[cpu-cycles] / [instructions]",
+		"expression-txn": "[cpu-cycles] / [TXN]"
     },
     {
         "name": "metric_kernel_CPI",
+		"name-txn": "metric_kernel_cycles per txn",
         "expression": "[cpu-cycles:k] / [instructions:k]",
+		"expression-txn": "[cpu-cycles:k] / [TXN]",
         "origin": "perfspect"
     },
     {
         "name": "metric_IPC",
+		"name-txn": "metric_txn per cycles",
         "expression": "[instructions] / [cpu-cycles]",
+		"expression-txn": "[instructions] / [TXN]",
         "origin": "perfspect"
     },
     {
@@ -33,36 +39,52 @@
     },
     {
         "name": "metric_locks retired per instr",
+		"name-txn": "metric_locks retired per txn",
         "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]",
+		"expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]",
         "origin": "perfmon website"
     },
     {
         "name": "metric_L1D MPI (includes data+rfo w/ prefetches)",
-        "expression": "[L1D.REPLACEMENT] / [instructions]"
+		"name-txn": "metric_L1D misses per txn (includes data+rfo w/ prefetches)",
+        "expression": "[L1D.REPLACEMENT] / [instructions]",
+		"expression-txn": "[L1D.REPLACEMENT] / [TXN]"
     },
     {
         "name": "metric_L1D demand data read hits per instr",
-        "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]"
+		"name-txn": "metric_L1D demand data read hits per txn",
+        "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]",
+		"expression-txn": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]"
     },
     {
         "name": "metric_L1-I code read misses (w/ prefetches) per instr",
-        "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]"
+		"name-txn": "metric_L1I code read misses (includes prefetches) per txn",
+        "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]",
+		"expression-txn": "[L2_RQSTS.ALL_CODE_RD] / [TXN]"
     },
     {
         "name": "metric_L2 demand data read hits per instr",
-        "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]"
+		"name-txn": "metric_L2 demand data read hits per txn",
+        "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]",
+		"expression-txn": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]"
     },
     {
         "name": "metric_L2 MPI (includes code+data+rfo w/ prefetches)",
-        "expression": "[L2_LINES_IN.ALL] / [instructions]"
+		"name-txn": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)",
+        "expression": "[L2_LINES_IN.ALL] / [instructions]",
+		"expression-txn": "[L2_LINES_IN.ALL] / [TXN]"
     },
     {
         "name": "metric_L2 demand data read MPI",
-        "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]"
+		"name-txn": "metric_L2 demand data read misses per txn",
+        "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]",
+		"expression-txn": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]"
     },
     {
         "name": "metric_L2 demand code MPI",
-        "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]"
+		"name-txn": "metric_L2 demand code misses per txn",
+        "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]",
+		"expression-txn": "[L2_RQSTS.CODE_RD_MISS] / [TXN]"
     },
     {
         "name": "metric_Average LLC data read miss latency (in clks)",
@@ -138,19 +160,27 @@
     },
     {
         "name": "metric_LLC code read MPI (demand+prefetch)",
-        "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [instructions]"
+		"name-txn": "metric_LLC code read (demand+prefetch) misses per txn",
+        "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [instructions]",
+		"expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [TXN]"
     },
     {
         "name": "metric_LLC data read MPI (demand+prefetch)",
-        "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]"
+		"name-txn": "metric_LLC data read (demand+prefetch) misses per txn",
+        "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]",
+		"expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]"
     },
     {
         "name": "metric_LLC total HITM (per instr) (excludes LLC prefetches)",
-        "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]"
+		"name-txn": "metric_LLC total HITM per txn (excludes LLC prefetches)",
+        "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]",
+		"expression-txn": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]"
     },
     {
         "name": "metric_LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)",
-        "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]"
+		"name-txn": "metric_LLC total HIT clean line forwards per txn (excludes LLC prefetches)",
+        "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]",
+		"expression-txn": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]"
     },
     {
         "name": "metric_Average LLC demand data read miss latency (in ns)",
@@ -166,19 +196,27 @@
     },
     {
         "name": "metric_ITLB (2nd level) MPI",
-        "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]"
+		"name-txn": "metric_ITLB (2nd level) misses per txn",
+        "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]",
+		"expression-txn": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]"
     },
     {
         "name": "metric_DTLB (2nd level) load MPI",
-        "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]"
+		"name-txn": "metric_DTLB (2nd level) load misses per txn",
+        "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]",
+		"expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]"
     },
     {
         "name": "metric_DTLB (2nd level) 2MB large page load MPI",
-        "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]"
+		"name-txn": "metric_DTLB (2nd level) 2MB large page load misses per txn",
+        "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]",
+		"expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]"
     },
     {
         "name": "metric_DTLB (2nd level) store MPI",
-        "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]"
+		"name-txn": "metric_DTLB (2nd level) store misses per txn",
+        "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]",
+		"expression-txn": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]"
     },
     {
         "name": "metric_NUMA %_Reads addressed to local DRAM",
@@ -356,4 +394,4 @@
         "name": "metric_TMA_Info_System_SMT_2T_Utilization",
         "expression": "1 - [CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE] / [CPU_CLK_UNHALTED.REF_DISTRIBUTED] if [SOCKET_COUNT] > 1 else 0"
     }
-]
+]