bcm283x: Implement bit stream functions, not enabled yet. #207
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- Based on @maruel's implementation. - DMA driven stream shares a fixed PWM and DREQ clock. Oversampling is used to get desired resolution.
Codecov Report
@@ Coverage Diff @@
## master #207 +/- ##
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- Coverage 83.97% 80.27% -3.7%
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Files 66 68 +2
Lines 5515 5811 +296
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+ Hits 4631 4665 +34
- Misses 761 1021 +260
- Partials 123 125 +2
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| return err | ||
| } | ||
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| // The first channel must be a full bandwidth one. |
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@maruel Could you explain why?
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Because the "light" ones are effectively a single one, which means that they are interleaved. If both are "light" then the jitter is largely increased.
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I experimented dual channel method but it seems that two channels easily get out of sync. I guess it DREQ clock can be missed.
maruel
changed the title
maruel
changed the title
| runIO(pCB, l <= maxLite) | ||
| // We have to wait PCM to be finished even after DMA finished. | ||
| for pcmMemory.cs&pcmTXErr == 0 { | ||
| Nanospin(10 * time.Nanosecond) |
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In theory it should try to wait the exact right amount of time.
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Yeah, I just wanted avoid a busy loop. Maybe, we should wait 1 PCM clock.
dmaChannel.wait() is a busy loop now.
| for i, ch := range dmaMemory.channels { | ||
| fmt.Println(i, ch.cs.String()) | ||
| if ch.cs&dmaActive != 0 { | ||
| fmt.Printf("%x: %s", ch.cbAddr, ch.GoString()) |
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I'd prefer log instead of fmt
used to get desired resolution.