About

Develop for Sipeed Tang Nano 20k following Gisselquist's Verilog, Formal Verification and Verilator Beginner's Tutorial

Requirements

• oss-cad-suite (or at least sby)
• verilator

What's inside?

Verilog, Formal Verification and Verilator Beginner's Tutorial

• Verilog, Formal Verification and Verilator Beginner's Tutorial

Formal Verification Courseware

• Formal Verification Courseware

Intermediate Verilog Tutorial

• Intermediate Verilog Tutorial ⚠ WIP ⚠

AMBA APB Bus

• Added formally verified apb_master.v in /projects/apb
• Working on formally verifying apb_slave.v in /projects/apb
• Working on formally verifying apb_top.v in /projects/apb to verify both master and slave together