ethernet: load divider.sv via symlink

fischermoseley · Nov 27, 2024 · e1ac698 · e1ac698
1 parent b993a4c
commit e1ac698
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv
@@ -0,0 +1 @@
+../../../common/divider.sv
diff --git a/test/test_ethernet_interface.py b/test/test_ethernet_interface.py
@@ -1,13 +1,15 @@
-import pytest
 import time
 from random import getrandbits
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
 from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 
 from manta import *
 from manta.utils import *
 
+
 class EthernetMemoryCoreTest(Elaboratable):
     def __init__(self, platform):
         self.platform = platform
@@ -102,7 +104,6 @@ def verify(self):
                 )
 
 
-
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
 def test_mem_core_xilinx():
-    EthernetMemoryCoreTest(Nexys4DDRPlatform()).verify()
+    EthernetMemoryCoreTest(Nexys4DDRPlatform()).verify()