uart: remove flaky nexys4ddr baudrate mismatch test case

fischermoseley · Oct 6, 2024 · 7eb5612 · 7eb5612
1 parent 783f29d
commit 7eb5612
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/test/test_uart_baud_mismatch.py b/test/test_uart_baud_mismatch.py
@@ -103,7 +103,6 @@ def test_baudrate_mismatch_xilinx_passes(baudrate, percent_slowdown, stall_inter
 
 
 nexys4ddr_fail_cases = [
-    (3e6, 1, 1024),  # Light clock mismatch, no mitigation
     (3e6, 2, 1024),  # Heavy clock mismatch, no mitigation
     (3e6, 2, 16),  # Heavy clock mismatch, light mitigation
 ]