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feat: reset KVM_REG_ARM_PTIMER_CNT on VM boot #4987

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@ShadowCurse ShadowCurse commented Jan 10, 2025

Reset KVM_REG_ARM_PTIMER_CNT physical counter register on VM boot to avoid passing through host physical counter. Note that resetting the register on VM boot does not guarantee that VM will see the counter value 0 at startup because there is a delta in time between register reset and VM boot during which counter continues to advance.

Reason

Prevent guest from reading host performance counter.

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CONTRIBUTING.md.

PR Checklist

  • I have read and understand CONTRIBUTING.md.
  • I have run tools/devtool checkstyle to verify that the PR passes the
    automated style checks.
  • I have described what is done in these changes, why they are needed, and
    how they are solving the problem in a clear and encompassing way.
  • I have updated any relevant documentation (both in code and in the docs)
    in the PR.
  • I have mentioned all user-facing changes in CHANGELOG.md.
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  • This functionality cannot be added in rust-vmm.

@ShadowCurse ShadowCurse force-pushed the aarch64_counter_reset branch from b34d97d to b459ae3 Compare January 10, 2025 13:11
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codecov bot commented Jan 10, 2025

Codecov Report

Attention: Patch coverage is 83.33333% with 1 line in your changes missing coverage. Please review.

Project coverage is 83.95%. Comparing base (a5ffb7a) to head (b5be991).

Files with missing lines Patch % Lines
src/vmm/src/arch/aarch64/vcpu.rs 83.33% 1 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main    #4987      +/-   ##
==========================================
- Coverage   83.95%   83.95%   -0.01%     
==========================================
  Files         248      248              
  Lines       27839    27845       +6     
==========================================
+ Hits        23371    23376       +5     
- Misses       4468     4469       +1     
Flag Coverage Δ
5.10-c5n.metal 84.53% <ø> (+<0.01%) ⬆️
5.10-m5n.metal 84.51% <ø> (ø)
5.10-m6a.metal 83.79% <ø> (+<0.01%) ⬆️
5.10-m6g.metal 80.63% <83.33%> (+<0.01%) ⬆️
5.10-m6i.metal 84.50% <ø> (+<0.01%) ⬆️
5.10-m7g.metal 80.63% <83.33%> (+<0.01%) ⬆️
6.1-c5n.metal 84.53% <ø> (+<0.01%) ⬆️
6.1-m5n.metal 84.51% <ø> (ø)
6.1-m6a.metal 83.79% <ø> (ø)
6.1-m6g.metal 80.63% <83.33%> (+<0.01%) ⬆️
6.1-m6i.metal 84.50% <ø> (ø)
6.1-m7g.metal 80.63% <83.33%> (+<0.01%) ⬆️

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@ShadowCurse ShadowCurse force-pushed the aarch64_counter_reset branch 2 times, most recently from 1bd3f94 to 5ea2f4a Compare January 10, 2025 14:24
@ShadowCurse ShadowCurse changed the title feat: reset SYS_CNTPCT_EL0 on VM boot feat: reset KVM_REG_ARM_PTIMER_CNT on VM boot Jan 10, 2025
@ShadowCurse ShadowCurse force-pushed the aarch64_counter_reset branch 4 times, most recently from 75a7ec1 to 053f265 Compare January 10, 2025 15:19
@ShadowCurse ShadowCurse marked this pull request as ready for review January 10, 2025 15:20
@ShadowCurse ShadowCurse self-assigned this Jan 10, 2025
@ShadowCurse ShadowCurse added Status: Awaiting review Indicates that a pull request is ready to be reviewed Type: Fix Indicates a fix to existing code labels Jan 10, 2025
.set_one_reg(KVM_REG_ARM_PTIMER_CNT, &zero.to_le_bytes())
.is_err()
{
warn!("Unable to reset performance counter. VM will use host value instead.");
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I really don't think we should have warnings that the user cannot silence. Maybe we can only print this if running on 6.4 or newer? Rest lgtm

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I don't think this is needed to be silenced. 6.4 is not super new and as time goes on, the less users will use kernel which will print the warning. If we add option to silence this, we will have to have it until we deprecate it and this is more work to do.

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I'm not inclined to print a warning either. It is not quite expected that users running Firecracker on a supported kernel get a warning they cannot fix.

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Well, this is a warning and not an error. They are not meant to be "fixed" I think.
I can add a link to the patch series that added the needed fixes to the changelog and tell users to use kernel with this patches if they want to remove the warning.

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I am ok with warning, but if that's too unpalatable, can we keep it as info rather than dropping it?

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I was also thinking about making it info, but then only people who enable info log level will see it.

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how about we only warn if the KVM_CAP_COUNTER_OFFSET KVM capability is supported (meaning we are on a kernel where setting the registers should be possible)?

src/vmm/src/arch/aarch64/vcpu.rs Outdated Show resolved Hide resolved
src/vmm/src/arch/aarch64/vcpu.rs Show resolved Hide resolved
src/vmm/src/arch/aarch64/vcpu.rs Outdated Show resolved Hide resolved
.set_one_reg(KVM_REG_ARM_PTIMER_CNT, &zero.to_le_bytes())
.is_err()
{
warn!("Unable to reset performance counter. VM will use host value instead.");
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I'm not inclined to print a warning either. It is not quite expected that users running Firecracker on a supported kernel get a warning they cannot fix.

src/vmm/src/arch/aarch64/regs.rs Show resolved Hide resolved
CHANGELOG.md Outdated Show resolved Hide resolved
Reset KVM_REG_ARM_PTIMER_CNT physical counter register on VM boot
to avoid passing through host physical counter.
Note that resetting the register on VM boot does not guarantee
that VM will see the counter value 0 at startup because there is
a delta in time between register reset and VM boot during which
counter continues to advance.

Signed-off-by: Egor Lazarchuk <[email protected]>
@ShadowCurse ShadowCurse force-pushed the aarch64_counter_reset branch from 053f265 to d3abf67 Compare January 10, 2025 16:26
Add an entry about physical counter reset to the CHANGELOG.

Signed-off-by: Egor Lazarchuk <[email protected]>
@ShadowCurse ShadowCurse force-pushed the aarch64_counter_reset branch from d3abf67 to 57b458b Compare January 10, 2025 16:31
@@ -238,6 +257,15 @@ mod tests {
vcpu.vcpu_init(&kvi).unwrap();

setup_boot_regs(&vcpu, 0, 0x0, &mem).unwrap();

// Check that the register is reset on compatible kernels.
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Can we also add an integration test in tests/integration_tests/security?

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Integration test will be quite difficult as we will need kernel access to read the physical counter.

Update a note about physical counter on ARM being reset instead of
directly passed through.

Signed-off-by: Egor Lazarchuk <[email protected]>
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