Partially support CSRRW where source and destination register is zero

ethereum-optimism · Jan 13, 2025 · 02f4b12 · 02f4b12
1 parent 4f45fbd
commit 02f4b12
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Showing 5 changed files with 36 additions and 4 deletions.
diff --git a/rvgo/fast/vm.go b/rvgo/fast/vm.go
@@ -866,8 +866,18 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
 			default: // imm12 = 000000000001 EBREAK
 				setPC(add64(pc, toU64(4))) // ignore breakpoint
 			}
-		default: // CSR instructions
-			setRegister(rd, 0) // ignore CSR instructions
+		case 1:
+			// CSRRW
+			rs1Value := getRegister(rs1)
+			rdValue := add64(pc, toU64(4))
+			// no source or destination registers must be specified
+			if or64(rs1Value, rdValue) != 0 {
+				revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("only no-op CSRRW instruction are supported"))
+			}
+			setRegister(rd, 0)
+			setPC(add64(pc, toU64(4)))
+		default:
+			setRegister(rd, 0) // ignore other CSR instructions
 			setPC(add64(pc, toU64(4)))
 		}
 	case 0x2F: // 010_1111: RV32A and RV32A atomic operations extension

diff --git a/rvgo/riscv/constants.go b/rvgo/riscv/constants.go
@@ -51,6 +51,7 @@ const (
 	ErrUnexpectedRProofLoad           = uint64(0xbad22220)
 	ErrUnexpectedRProofStoreUnaligned = uint64(0xbad22221)
 	ErrUnexpectedRProofStore          = uint64(0xbad2222f)
+	ErrIllegalInstruction             = uint64(0xbadc0de)
 	ErrBadAMOSize                     = uint64(0xbada70)
 	ErrFailToReadPreimage             = uint64(0xbadf00d0)
 	ErrBadMemoryProof                 = uint64(0xbadf00d1)

diff --git a/rvgo/slow/vm.go b/rvgo/slow/vm.go
@@ -1050,7 +1050,17 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
 			default: // imm12 = 000000000001 EBREAK
 				setPC(add64(pc, toU64(4))) // ignore breakpoint
 			}
-		default: // ignore CSR instructions
+		case 1:
+			// CSRRW
+			rs1Value := getRegister(rs1)
+			rdValue := getRegister(rd)
+			// no source or destination registers must be specified
+			if or64(rs1Value, rdValue) != (U64{}) {
+				revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("only no-op CSRRW instruction are supported"))
+			}
+			setRegister(rd, toU64(0))
+			setPC(add64(pc, toU64(4)))
+		default: // ignore other CSR instructions
 			setRegister(rd, toU64(0)) // ignore CSR instructions
 			setPC(add64(pc, toU64(4)))
 		}

diff --git a/rvsol/src/RISCV.sol b/rvsol/src/RISCV.sol
@@ -1542,6 +1542,17 @@ contract RISCV is IBigStepper {
                         setPC(add64(_pc, toU64(4))) // ignore breakpoint
                     }
                 }
+                case 1 {
+                    // CSRRW
+                    let rs1Value := getRegister(rs1)
+                    let rdValue := getRegister(rd)
+
+                    // no source or destination registers must be specified
+                    if or64(rs1Value, rdValue) { revertWithCode(0xbadc0de) }
+
+                    setRegister(rd, toU64(0))
+                    setPC(add64(_pc, toU64(4)))
+                }
                 default {
                     // CSR instructions
                     setRegister(rd, toU64(0)) // ignore CSR instructions

diff --git a/rvsol/test/RISCV.t.sol b/rvsol/test/RISCV.t.sol
@@ -1801,7 +1801,7 @@ contract RISCV_Test is CommonTest {
 
     function test_csrrw_succeeds() public {
         uint16 imm = 0x29a;
-        uint32 insn = encodeIType(0x73, 13, 1, 2, imm); // csrrw x13, 0x29a, x2
+        uint32 insn = encodeIType(0x73, 0x0, 0x1, 0x0, imm); // csrrw 0x0, 0x29a, 0x0
         (State memory state, bytes memory proof) = constructRISCVState(0, insn);
         state.registers[2] = 0x4797;
         bytes memory encodedState = encodeState(state);