esp-18.1.2_20240912

Changes since esp-18.1.2_20240829:

Fixes:

• [Xtensa] Fix atomic store operands order. In LLVM 18 atomic store operands order was changed https://reviews.llvm.org/D123143.

esp-18.1.2_20240829

Changes since esp-18.1.2_20240815:

Fixes:

• [RISCV] Fixed registers class for esp32p4 HW loop instructions. Removed unnecessary registers operands limits for HW loop instructions.
• [Toolchain][Espressif] Added 'xesppie' multilib variant mapping for esp32p4. Fixed warning: no multilib found matching flags when xesppie extension is enabled.
• [RISCV][ESP32P4] Don't yet consider v16i8 and v4i32 legal. W/o this fix Clang crashed when tried to select instruction for v16i8 and v4i32 types.

esp-18.1.2_20240815

Changes since esp-17.0.1_20240419:

Features:

• Upgraded LLVM ver to 18.1.2.
• [RISCV] Support for ESP32-P4 custom instructions in RISCV backend.
• [RISCV] Add support for user trap CSRs.
• [Xtensa] Added support for asm underscore prefix which prevents assembler from replacing instructions with their equivalents (single or multiple instructions) when it is applicable.

esp-17.0.1_20240419

Changes (since esp-17.0.1_20240408):

Fixes:

• [Xtensa] Fix issue with adding scavenging frame index. Fixes bug introduced in 50f918b which led to missed spill slot and error like LLVM ERROR: Error while trying to spill A9 from class AR: Cannot scavenge register without an emergency spill slot!.
• [Toolchain][Espressif] Include clangd into distribution. Close #93

esp-17.0.1_20240408

Changes (since esp-16.0.4-20231113):

Features:

• Upgraded LLVM ver to 17.0.1.
• [Toolchain][Espressif]: Upgraded binutils version to 'esp-2.41.0_20240305'.
• [Toolchain][Espressif]: Upgraded newlib version to 'esp-4.3.0_20240322'.
• [Toolchain][Espressif]: Upgraded libstdc++ and libgcc to '13.2.0_20240305'.
• [Toolchain][RISCV][Xtensa] Added Espressif baremetal toolchain.
• [Toolchain][RISCV][Xtensa] Removed GCC installation support for Espressif toolchain. Now picking up multilibs from existing GCC installation is not possible.
• [RISCV] Add 'tcontrol' CSR register.
• [Xtensa] Add predefined macros for core configuration. Now every configrable option for Xtensa core can be checked using pre-defined macro as it is done in GCC 13.
• [Xtensa] Implement support for __attribute__((short__call)) and __attribute__((near)). Related to #90.
• [Xtensa] Add vector conversion builtins. Closes #89.
• [Xtensa] Add support for boolean vectors. Closes #89.
• [Xtensa] Add HIFI3 C types and intrinsics. Closes #89.
• [Xtensa] Add HIFI3 target feature. Closes #89.
• [Xtensa] Make assembler output compatible with GAS. Some Xtensa targets may still use GAS as a default assembler through '-fno-integrated-as option'. These changes make the assembly output compatible with GAS by default.
• [Xtensa] Add Cannonlake CPU. Added a definition of Xtensa LX6 CPU variant present in Intel Cannonlake and Tigerlake SOC platforms. Closes #89.
• [Xtensa] Add float intrinsics. Closes #89.
• [Xtensa] Implement conditional move instrinsics. Closes #89.
• [Xtensa] Add Boolean Extension feature. Closes #89.
• [Xtensa] Add definition of S3 output registers. Xtensa S3 DSP instructions are coded using explicit register allocation. However, some instructions miss RegState:Define flag for output registers. This leads MachineVerifier to raise errors.

Bug Fixes:

• [Toolchain][Espressif] Use custom prefixes for 'as' and 'ld'. To avoid conflicts with 'as' and 'ld' installed as part of IDF GCC-based toolchains. These tools will be replaced with integrated assembler and LLD in future.
• [LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3.
• [Xtensa] Fix disassembler. Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands.
• [Clang] Fix undefined std::errc::state_not_recoverable for MinGW build. Replaced with std::errc::not_supported error code.

esp-16.0.4-20231113

Changes (since esp-16.0.0-20230516):

Features:

• Rebased on LLVM 16.0.4
• [Xtensa] Implement CTLZ/CTTZ with NSAU. Closes #77.
• [Xtensa] Handle musttail. Closes #73.
• [Xtensa] Add MINMAX and CLAMPS feature. Closes #78.
• [Xtensa] Add support for ESP32 S3 DSP instructions. The instructions are supported via clang builtins only, which are basically 1-1 mapping to asm instructions.
• [Xtensa] Connect abs to llvm.abs. Closes #78.
• [Xtensa] Configurable FAST int types size. Implemented special option -mfast-int-min32 to workaround compatibility problem with Xtensa GCC's backend which defines size of FAST int types as 4 bytes.

Bug Fixes:

• [Xtensa] Add spill slot for smaller estimated stack size.
• [Xtensa] Fix wchar type. Previously wchar was internally represented as unsigned char. Now it is represented as signed int.
• [Xtensa] Add absent IR passes. Added common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.
• [Xtensa] Fix Clang builtins include directory. Fixes #83. Closes #84.
• [LLD][Xtensa] Improve literal sections placement. Literal sections are now put as close as possible to appropriate text sections.
• Get back [Xtensa] Fixes HW loop pass f389074 which was lost during rebase on LLVM 16.0.0. See details about the fix in esp-15.0.0-20230404 release notes.
• [Xtensa] Fix FP mul-sub fusion. Closes #76.
• [Xtensa] Fix asm parsing of special interrupt registers names. Fixes #68. Closes #69
• [Xtensa] Fix i8/i16 alignment. Change preferable alignment for i8 and i16 types on stack to 32-bit.
• [LLD][Xtensa] Recognize bt instruction in lld.
• [Xtensa] Respect srli assembler semantics. Fixes #70.

esp-16.0.0-20230516

Changes (since esp-15.0.0-20230404):

Features:

• Upgraded LLVM version to 16.0.0.
• Added support for complier-rt library. Now toolchain is supplied with complier-rt library. complier-rt multilib feature is supported for RISCV and Xtensa targets.
• Built newlib with -ffunction-sections and -fdata-sections flags.
• [Xtensa] Implemented __ieee754_sqrtf builtin.

Bug Fixes:

• [Xtensa] Fix i8/i16 ABI alignment. Fixes problem reported in #66.

esp-15.0.0-20230404

Changes (since esp-15.0.0-20221201):

Features:

• [Xtensa] Implements constant islands pass. For large code models it allows to intersperse code with constants, because sometimes L32R instruction range in immediate field is not enough.
• [LLD][Xtensa] Cover DIFF{8, 16, 32} relocations.
• [Xtensa] Improves fixup error messages in asm backend. Adds different diagnostic messages for different branch
  relocation fixups.

Bug Fixes:

• [Xtensa] Fixes HW loop pass. Fixes HW loop miscompilation with opt-level = 's'. See esp-rs/rust#164
• [Xtensa] Disables hardware loops by default.

esp-15.0.0-20221201

Changes (since esp-15.0.0-20221014):

Features:

• [Xtensa] Add LLD linker support.
• [Xtensa] Add support for -mtext-section-literals option. See description of the same option in GNU assembler.
• [Xtensa] Add support of the -mcmodel=large option. Currently it just enables -mtext-section-literals.
• Removed dependency on terminfo library. Previous release for Linux systems had a dependency on libtinfo5 which is pretty old version.
• Added nano versions of libc, libm and libg to toolchain.

Bug Fixes:

• [Xtensa] Fixed lowering funnel shift left. Previous implementation generated incorrect Xtensa instruction sequence.
• [Xtensa] Made it possible to use -fuse-ld when GCC toolchain is detected. Previosuly toolchain always used GNU xtensa linker.

esp-15.0.0-20221014

Changes (since esp-14.0.0-20220415):

Features:

• Upgrade LLVM version to 15.0.0
• Single toolchain for any Espressif chip (either Xtensa or RISCV architectures)
• Distribution for Linux ARM and ARM64 platforms. Closes #61.
• Distribution for MacOS ARM64 platform. Closes #61.
• Minimal distributions including libraries and headers only to be used by 3rd party tools (e.g. Espressif Rust port)
• Support Espressif vendor in target triple: xtensa-esp-elf and riscv32-esp-elf

Bug Fixes:

• [Xtensa] Fixes broken inline assembly memory operands. Closes #58.
• [Xtensa] Expand addi instruction with large immediate, to addmi + addi.
• [Xtensa] Implement support of .literal and .region directives in assembler parser.
• [Xtensa] Add bbci.l macro for bbci instruction and bbsi.l for bbsi.
• [Xtensa] Fix ill.n instruction encoding
• [Xtensa] Implement support of the --sysroot clang option. Closes #56.