Merge branch 'feature/esp_p4_as_mcu_host' into 'feature/esp_as_mcu_host'

feature/p4_as_mcu_host Add ESP32-P4 as MCU host See merge request app-frameworks/esp_hosted!382
espressif · Jan 23, 2024 · 000e337 · 000e337
2 parents 835a667 + 4842f52
commit 000e337
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Showing 9 changed files with 155 additions and 77 deletions.
diff --git a/Kconfig b/Kconfig
@@ -9,6 +9,7 @@ menu "ESP-Hosted config"
 	choice ESP_HOST_INTERFACE
 		bool "Transport layer"
 		default ESP_SDIO_HOST_INTERFACE if IDF_TARGET_ESP32
+		default ESP_SDIO_HOST_INTERFACE if IDF_TARGET_ESP32P4
 		default ESP_SPI_HOST_INTERFACE
 		help
 			Bus interface to be used for communication with the host
@@ -20,7 +21,7 @@ menu "ESP-Hosted config"
 
 		config ESP_SDIO_HOST_INTERFACE
 			bool "SDIO interface"
-				depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
+				depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4
 			help
 				Enable/Disable SDIO host interface
 	endchoice
@@ -318,8 +319,22 @@ ESP32XX_SPI_CLK_FREQ_RANGE_MAX := 40
 		menu "Hosted SDIO Configuration"
 			depends on ESP_SDIO_HOST_INTERFACE
 
+			choice SDIO_RESET_GPIO_CONFIG
+				bool "RESET GPIO Config"
+				default SDIO_RESET_ACTIVE_HIGH
+				help
+					"If Active High, High->Low->High will trigger reset (Low will trigger reset)
+					 If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
+
+				config SDIO_RESET_ACTIVE_HIGH
+					bool "RESET: Active High"
+				config SDIO_RESET_ACTIVE_LOW
+					bool "RESET: Active Low"
+			endchoice
+
 			config ESP_SDIO_GPIO_RESET_SLAVE
 				int "GPIO pin for Reseting slave ESP"
+				default 54 if IDF_TARGET_ESP32P4
 				default 5
 				help
 					GPIO pin for Resetting ESP SDIO slave device. Should be connected to RST/EN of ESP SDIO slave device.
@@ -346,6 +361,8 @@ ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
 ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 40000
 ESP32S3_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
 ESP32S3_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 80000
+ESP32P4_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
+ESP32P4_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 80000
 
 			config ESP_SDIO_FREQ_ESP32
 				depends on IDF_TARGET_ESP32
@@ -363,37 +380,50 @@ ESP32S3_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 80000
 				help
 					"Optimize SDIO CLK by increasing till host practically can support"
 
+			config ESP_SDIO_FREQ_ESP32P4
+				depends on IDF_TARGET_ESP32P4
+				int "SDIO Clock Freq (in KHz)"
+				default 40000
+				range $(ESP32P4_SDIO_CLK_FREQ_KHZ_RANGE_MIN) $(ESP32P4_SDIO_CLK_FREQ_KHZ_RANGE_MAX)
+				help
+					"Optimize SDIO CLK by increasing till host practically can support"
+
 			config ESP_SDIO_CLOCK_FREQ
 				int
 				default ESP_SDIO_FREQ_ESP32 if IDF_TARGET_ESP32
 				default ESP_SDIO_FREQ_ESP32S3 if IDF_TARGET_ESP32S3
+				default ESP_SDIO_FREQ_ESP32P4 if IDF_TARGET_ESP32P4
 				help
 					"Optimize SDIO CLK by increasing till host practically can support"
 
 			config ESP_SDIO_PIN_CMD
 				int "CMD GPIO number"
 				default 35 if IDF_TARGET_ESP32S3
+				default 19 if IDF_TARGET_ESP32P4
 				range 15 15 if IDF_TARGET_ESP32
 				help
 					"Value can only be configured for some targets. Displayed always for reference."
 
 			config ESP_SDIO_PIN_CLK
 				int "CLK GPIO number"
 				default 36 if IDF_TARGET_ESP32S3
+				default 18 if IDF_TARGET_ESP32P4
 				range 14 14 if IDF_TARGET_ESP32
 				help
 					"Value can only be configured for some targets. Displayed always for reference."
 
 			config ESP_SDIO_PIN_D0
 				int "D0 GPIO number"
 				default 37 if IDF_TARGET_ESP32S3
+				default 49 if IDF_TARGET_ESP32P4
 				range 2 2 if IDF_TARGET_ESP32
 				help
 					"Value can only be configured for some targets. Displayed always for reference."
 
 			config ESP_SDIO_PIN_D1
 				int "D1 GPIO number"
 				default 38 if IDF_TARGET_ESP32S3
+				default 50 if IDF_TARGET_ESP32P4
 				range 4 4 if IDF_TARGET_ESP32
 				help
 					"Value can only be configured for some targets. Displayed always for reference."
@@ -402,13 +432,15 @@ ESP32S3_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 80000
 				config ESP_SDIO_PIN_D2
 					int "D2 GPIO number"
 					default 33 if IDF_TARGET_ESP32S3
+					default 16 if IDF_TARGET_ESP32P4
 					range 12 12 if IDF_TARGET_ESP32
 					help
 						"Value can only be configured for some targets. Displayed always for reference."
 
 				config ESP_SDIO_PIN_D3
 					int "D3 GPIO number"
 					default 34 if IDF_TARGET_ESP32S3
+					default 17 if IDF_TARGET_ESP32P4
 					range 13 13 if IDF_TARGET_ESP32
 					help
 						"Value can only be configured for some targets. Displayed always for reference."
@@ -438,6 +470,11 @@ ESP32S3_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 80000
 			default ESP_SPI_GPIO_RESET_SLAVE if ESP_SPI_HOST_INTERFACE
 			default ESP_SDIO_GPIO_RESET_SLAVE if ESP_SDIO_HOST_INTERFACE
 
+		config RESET_GPIO_ACTIVE_LOW
+			bool
+			default n if SDIO_RESET_ACTIVE_HIGH || SPI_RESET_ACTIVE_HIGH
+			default y if SDIO_RESET_ACTIVE_LOW || SPI_RESET_ACTIVE_LOW
+
 	config ESP_USE_MEMPOOL
 		bool "Cache allocated memory like mempool - helps to reduce malloc calls"
 		default y

diff --git a/host/drivers/mempool/mempool.c b/host/drivers/mempool/mempool.c
@@ -16,13 +16,14 @@
 #include "mempool.h"
 #include "esp_hosted_config.h"
 #include "stats.h"
+#include "esp_log.h"
 #define MEMPOOL_DEBUG 1
 
 
+static char * MEM_TAG = "mpool";
 #if H_MEM_STATS
 #include "esp_log.h"
 
-static char * MEM_TAG = "mpool";
 
 #endif
 
@@ -48,7 +49,7 @@ struct mempool * mempool_create(uint32_t block_size)
 		return NULL;
 	}
 
-    new->spinlock = g_h.funcs->_h_create_lock_mempool();
+	new->spinlock = g_h.funcs->_h_create_lock_mempool();
 
 	new->block_size = MEMPOOL_ALIGNED(block_size);
 	SLIST_INIT(&(new->head));
@@ -111,7 +112,7 @@ void * mempool_alloc(struct mempool* mp, int nbytes, int need_memset)
 
 		g_h.funcs->_h_unlock_mempool(mp->spinlock);
 
-		buf = MEM_ALLOC(mp->block_size);
+		buf = MEM_ALLOC(MEMPOOL_ALIGNED(mp->block_size));
 #if H_MEM_STATS
 		h_stats_g.mp_stats.num_fresh_alloc++;
 		ESP_LOGV(MEM_TAG, "%p: num_alloc: %lu", mp, (unsigned long int)(h_stats_g.mp_stats.num_fresh_alloc));
@@ -120,6 +121,7 @@ void * mempool_alloc(struct mempool* mp, int nbytes, int need_memset)
 #else
 	buf = MEM_ALLOC(MEMPOOL_ALIGNED(nbytes));
 #endif
+	ESP_LOGV(MEM_TAG, "alloc %u bytes at %p", nbytes, buf);
 
 	if (buf && need_memset)
 		g_h.funcs->_h_memset(buf, 0, nbytes);
@@ -152,4 +154,3 @@ void mempool_free(struct mempool* mp, void *mem)
 	g_h.funcs->_h_free(mem);
 #endif
 }
-
diff --git a/host/drivers/mempool/mempool.h b/host/drivers/mempool/mempool.h
@@ -20,7 +20,7 @@
 
 #define MEMPOOL_NAME_STR_SIZE            32
 
-#define MEMPOOL_ALIGNMENT_BYTES          4
+#define MEMPOOL_ALIGNMENT_BYTES          64
 #define MEMPOOL_ALIGNMENT_MASK           (MEMPOOL_ALIGNMENT_BYTES-1)
 #define IS_MEMPOOL_ALIGNED(VAL)          (!((VAL)& MEMPOOL_ALIGNMENT_MASK))
 #define MEMPOOL_ALIGNED(VAL)             ((VAL) + MEMPOOL_ALIGNMENT_BYTES - \

diff --git a/host/drivers/transport/sdio/sdio_drv.c b/host/drivers/transport/sdio/sdio_drv.c
@@ -97,26 +97,26 @@ static void sdio_process_rx_task(void const* pvParameters);
 
 static inline void sdio_mempool_create()
 {
-    MEM_DUMP("sdio_mempool_create");
-    buf_mp_g = mempool_create(MAX_SDIO_BUFFER_SIZE);
+	MEM_DUMP("sdio_mempool_create");
+	buf_mp_g = mempool_create(MAX_SDIO_BUFFER_SIZE);
 #ifdef CONFIG_ESP_CACHE_MALLOC
-    assert(buf_mp_g);
+	assert(buf_mp_g);
 #endif
 }
 
 static inline void sdio_mempool_destroy()
 {
-    mempool_destroy(buf_mp_g);
+	mempool_destroy(buf_mp_g);
 }
 
 static inline void *sdio_buffer_alloc(uint need_memset)
 {
-    return mempool_alloc(buf_mp_g, MAX_SDIO_BUFFER_SIZE, need_memset);
+	return mempool_alloc(buf_mp_g, MAX_SDIO_BUFFER_SIZE, need_memset);
 }
 
 static inline void sdio_buffer_free(void *buf)
 {
-    mempool_free(buf_mp_g, buf);
+	mempool_free(buf_mp_g, buf);
 }
 
 void transport_deinit_internal(void)
@@ -401,8 +401,8 @@ static int is_valid_sdio_rx_packet(uint8_t *rxbuff_a, uint16_t *len_a, uint16_t
 	offset = le16toh(h->offset);
 
 	if ((!len) ||
-	    (len > MAX_PAYLOAD_SIZE) ||
-	    (offset != sizeof(struct esp_payload_header))) {
+		(len > MAX_PAYLOAD_SIZE) ||
+		(offset != sizeof(struct esp_payload_header))) {
 
 		/* Free up buffer, as one of following -
 		 * 1. no payload to process
@@ -461,10 +461,10 @@ static void sdio_read_task(void const* pvParameters)
 
 	// wait for transport to be in reset state
 	while (true) {
+		vTaskDelay(pdMS_TO_TICKS(100));
 		if (is_transport_rx_ready()) {
 			break;
 		}
-		vTaskDelay(pdMS_TO_TICKS(100));
 	}
 
 	res = g_h.funcs->_h_sdio_card_init(sdio_handle);

diff --git a/host/drivers/transport/transport_drv.c b/host/drivers/transport/transport_drv.c
@@ -61,11 +61,11 @@ static void reset_slave(void)
 	ESP_LOGI(TAG, "Reset slave using GPIO[%u]", H_GPIO_PIN_RESET_Pin);
 	g_h.funcs->_h_config_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_GPIO_MODE_DEF_OUTPUT);
 
-	g_h.funcs->_h_write_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_GPIO_HIGH);
-	g_h.funcs->_h_msleep(100);
-	g_h.funcs->_h_write_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_GPIO_LOW);
-	g_h.funcs->_h_msleep(100);
-	g_h.funcs->_h_write_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_GPIO_HIGH);
+	g_h.funcs->_h_write_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_RESET_VAL_ACTIVE);
+	g_h.funcs->_h_msleep(50);
+	g_h.funcs->_h_write_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_RESET_VAL_INACTIVE);
+	g_h.funcs->_h_msleep(50);
+	g_h.funcs->_h_write_gpio(H_GPIO_PIN_RESET_Port, H_GPIO_PIN_RESET_Pin, H_RESET_VAL_ACTIVE);
 
 	/* stop spi transactions short time to avoid slave sync issues */
 	g_h.funcs->_h_sleep(1);
@@ -301,15 +301,15 @@ transport_channel_t *transport_drv_add_channel(void *api_chan,
 	channel->rx = rx;
 
 	/* Need to change size wrt transport */
-    channel->memp = mempool_create(MAX_TRANSPORT_BUFFER_SIZE);
+	channel->memp = mempool_create(MAX_TRANSPORT_BUFFER_SIZE);
 #ifdef CONFIG_ESP_CACHE_MALLOC
-    assert(channel->memp);
+	assert(channel->memp);
 #endif
 
 	ESP_LOGI(TAG, "Add ESP-Hosted channel IF[%u]: S[%u] Tx[%p] Rx[%p]",
 			if_type, secure, *tx, rx);
 
-    return channel;
+	return channel;
 }
 
 void process_capabilities(uint8_t cap)
@@ -447,7 +447,7 @@ esp_err_t send_slave_config(uint8_t host_cap, uint8_t firmware_chip_id,
 	uint8_t raw_tp_cap = 0;
 	uint8_t *sendbuf = NULL;
 
-	sendbuf = malloc(500); /*Arbitrary number*/
+	sendbuf = malloc(512); /*Arbitrary number*/
 	assert(sendbuf);
 
 	/* Populate event data */
@@ -545,11 +545,11 @@ int process_init_event(uint8_t *evt_buf, uint16_t len)
 	}
 
 	if ((chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32) &&
-	    (chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32S2) &&
-	    (chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32C2) &&
-	    (chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32C3) &&
-	    (chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32C6) &&
-	    (chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32S3)) {
+		(chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32S2) &&
+		(chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32C2) &&
+		(chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32C3) &&
+		(chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32C6) &&
+		(chip_type != ESP_PRIV_FIRMWARE_CHIP_ESP32S3)) {
 		ESP_LOGI(TAG, "ESP board type is not mentioned, ignoring [%d]\n\r", chip_type);
 		chip_type = ESP_PRIV_FIRMWARE_CHIP_UNRECOGNIZED;
 		return -1;

diff --git a/host/port/esp_hosted_config.h b/host/port/esp_hosted_config.h
@@ -57,7 +57,7 @@ so feel free to change these if needed.
   #define H_DATAREADY_ACTIVE_HIGH 1
 #endif
 
-#ifdef H_HANDSHAKE_ACTIVE_HIGH
+#if H_HANDSHAKE_ACTIVE_HIGH
   #define H_HS_VAL_ACTIVE                            H_GPIO_HIGH
   #define H_HS_VAL_INACTIVE                          H_GPIO_LOW
   #define H_HS_INTR_EDGE                             H_GPIO_INTR_POSEDGE
@@ -67,7 +67,7 @@ so feel free to change these if needed.
   #define H_HS_INTR_EDGE                             H_GPIO_INTR_NEGEDGE
 #endif
 
-#ifdef H_DATAREADY_ACTIVE_HIGH
+#if H_DATAREADY_ACTIVE_HIGH
   #define H_DR_VAL_ACTIVE                            H_GPIO_HIGH
   #define H_DR_VAL_INACTIVE                          H_GPIO_LOW
   #define H_DR_INTR_EDGE                             H_GPIO_INTR_POSEDGE
@@ -165,6 +165,23 @@ so feel free to change these if needed.
 #define H_GPIO_PIN_RESET_Port                        NULL
 #define H_GPIO_PIN_RESET_Pin                         CONFIG_ESP_GPIO_SLAVE_RESET_SLAVE
 
+/* If Reset pin is Enable, it is Active High.
+ * If it is RST, active low */
+#ifdef CONFIG_RESET_GPIO_ACTIVE_LOW
+  #define H_RESET_ACTIVE_HIGH                           0
+#else
+  #define H_RESET_ACTIVE_HIGH                           1
+#endif
+
+#ifdef H_RESET_ACTIVE_HIGH
+  #define H_RESET_VAL_ACTIVE                            H_GPIO_HIGH
+  #define H_RESET_VAL_INACTIVE                          H_GPIO_LOW
+#else
+  #define H_RESET_VAL_ACTIVE                            H_GPIO_LOW
+  #define H_RESET_VAL_INACTIVE                          H_GPIO_HIGH
+#endif
+
+
 #define TIMEOUT_PSERIAL_RESP                         30