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Merge branch 'master' of https://github.com/emsec/hal
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joern274 committed Dec 2, 2020
2 parents 2242ce4 + 885ffc9 commit b25d3ff
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7 changes: 6 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -5,6 +5,10 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [Unreleased]
* added `NetlistSimulator::load_initial_value_from_netlist` to load the initial value from the netlist
* changed `NetlistSimulator::load_initial_values` to load a user-specified value instead of reading it from the netlist

## [3.1.8] - 2020-12-02 10:00:00+02:00 (urgency: medium)
* added optional placement of gates and modules according to COORDINATE info parsed from netlist file
* fixed bug in recently introduced placement according to parsed coordinates, map needs clear if unused
* fixed crash caused by NodeBoxes hash not completely emptied on clear
Expand Down Expand Up @@ -427,7 +431,8 @@ Note: This is an API breaking release.
* Initial Release

[//]: # (Hyperlink section)
[Unreleased]: https://github.com/emsec/hal/compare/v3.1.7...HEAD
[Unreleased]: https://github.com/emsec/hal/compare/v3.1.8...HEAD
[3.1.8]: https://github.com/emsec/hal/compare/v3.1.7...v3.1.8
[3.1.7]: https://github.com/emsec/hal/compare/v3.1.6...v3.1.7
[3.1.6]: https://github.com/emsec/hal/compare/v3.1.5...v3.1.6
[3.1.5]: https://github.com/emsec/hal/compare/v3.1.4...v3.1.5
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2 changes: 1 addition & 1 deletion CURRENT_VERSION
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@@ -1 +1 @@
3.1.7
3.1.8
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Expand Up @@ -69,11 +69,17 @@ namespace hal
void set_input(Net* net, SignalValue value);

/**
* Load the initial values for all sequential elements into the current state.
* For example, a Flip Flop may be initialized with HIGH output in FPGAs.
* This is not done automatically!
* Load the specified initial value into the current state of all sequential elements.
*
* @param[in] value - The initial value to load.
*/
void load_initial_values(SignalValue value);

/**
* Load the initial value specified within the netlist file into the current state of all sequential elements.
* This is especially relevant for FPGA netlists, since these may provide initial values to load on startup.
*/
void load_initial_values();
void load_initial_values_from_netlist();

/**
* Simulate for a specific period, advancing the internal state.
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13 changes: 9 additions & 4 deletions plugins/netlist_simulator/python/python_bindings.cpp
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Expand Up @@ -107,10 +107,15 @@ namespace hal
:param netlist_simulator.SignalValue value: The value to set.
)")

.def("load_initial_values", &NetlistSimulator::load_initial_values, R"(
Load the initial values for all sequential elements into the current state.
For example, a Flip Flop may be initialized with HIGH output in FPGAs.
This is not done automatically!
.def("load_initial_values", &NetlistSimulator::load_initial_values, py::arg("value"), R"(
Load the specified initial value into the current state of all sequential elements.
:param netlist_simulator.SignalValue value: The initial value to load.
)")

.def("load_initial_values_from_netlist", &NetlistSimulator::load_initial_values_from_netlist, R"(
Load the initial value specified within the netlist file into the current state of all sequential elements.
This is especially relevant for FPGA netlists, since these may provide initial values to load on startup.
)")

.def("simulate", &NetlistSimulator::simulate, py::arg("picoseconds"), R"(
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36 changes: 35 additions & 1 deletion plugins/netlist_simulator/src/netlist_simulator.cpp
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Expand Up @@ -87,7 +87,41 @@ namespace hal
m_event_queue.push_back(e);
}

void NetlistSimulator::load_initial_values()
void NetlistSimulator::load_initial_values(SignalValue value)
{
// has to work even if the simulation was not started, i.e., initialize was not called yet
// so we cannot use the SimulationGateFF type

for (auto gate : m_simulation_set)
{
if (gate->get_type()->get_base_type() == GateType::BaseType::ff)
{
auto gate_type = dynamic_cast<const GateTypeSequential*>(gate->get_type());

SignalValue inv_value = toggle(value);

// generate events
for (const auto& pin : gate_type->get_state_output_pins())
{
Event e;
e.affected_net = gate->get_fan_out_net(pin);
e.new_value = value;
e.time = m_current_time;
m_event_queue.push_back(e);
}
for (const auto& pin : gate_type->get_inverted_state_output_pins())
{
Event e;
e.affected_net = gate->get_fan_out_net(pin);
e.new_value = inv_value;
e.time = m_current_time;
m_event_queue.push_back(e);
}
}
}
}

void NetlistSimulator::load_initial_values_from_netlist()
{
// has to work even if the simulation was not started, i.e., initialize was not called yet
// so we cannot use the SimulationGateFF type
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8 changes: 4 additions & 4 deletions plugins/netlist_simulator/test/simulator_test.cpp
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Expand Up @@ -453,7 +453,7 @@ namespace hal

//prepare simulation
sim->add_gates(nl->get_gates());
sim->load_initial_values();
sim->load_initial_values_from_netlist();
auto A = *(nl->get_nets([](auto net) { return net->get_name() == "A"; }).begin());
auto B = *(nl->get_nets([](auto net) { return net->get_name() == "B"; }).begin());

Expand Down Expand Up @@ -523,7 +523,7 @@ namespace hal

//prepare simulation
sim->add_gates(nl->get_gates());
sim->load_initial_values();
sim->load_initial_values_from_netlist();

// retrieve nets
auto reset = *(nl->get_nets([](auto net) { return net->get_name() == "Reset"; }).begin());
Expand Down Expand Up @@ -608,7 +608,7 @@ namespace hal

//prepare simulation
sim->add_gates(nl->get_gates());
sim->load_initial_values();
sim->load_initial_values_from_netlist();

// retrieve nets
auto clk = *(nl->get_nets([](auto net) { return net->get_name() == "CLK"; }).begin());
Expand Down Expand Up @@ -752,7 +752,7 @@ namespace hal

//prepare simulation
sim->add_gates(nl->get_gates());
sim->load_initial_values();
sim->load_initial_values_from_netlist();

// retrieve nets
auto clk = *(nl->get_nets([](auto net) { return net->get_name() == "clk"; }).begin());
Expand Down

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