Support for CS active high #258
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CS lines can now be active high. Ideas taken from https://github.com/eblot/pyftdi/pull/86/files Main difference is that we can individually select which CS lines that shall be active high. This is done using a bitfield.
Property not needed - static bit mask better/faster.
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I have a proprietary device with active high CS line, and you PR gave me great service. Thank you very much for your job. It would be nice to see this feature merged. |
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Glad to hear that someone found it useful. I am in the same situation, I also need this for a proprietary design. I would also like to see it merged into the main project. |
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Will do but I think a couple of changes are required. I lack time at the moment :-( |
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No worries. And thanks for the time you have put into the project. |
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The main issue here is the CS initial bitmap meaning.
I think an iterable of CS lines to set high would be easier to use and less error prone, e.g.
cs_act_hi = [0, 2, 3] would tell to use CS0, CS2 and CS3 active high.
It should be cross-checked with the number of CS line (so an early error could be reported), and the cs_bits property would also return an iterable (list or set).
A minimal unit test would be nice as well, as least to check it does not break pre-existing implementation.
Thanks.
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I agree that an iterable is better, good idea. I looked at writing a small unit test, but it looked like the existing ones were designed to run against a particular hardware configuration (expects to find chips at different CS locations). Maybe I misunderstood? I wasn't sure how to proceed. I will take another look. |
More user friendly API for configuring active high CS lines. Can now check the configuration, both on the controller and on each port. Also add a minimal unit test that verifies we can set cs_act_hi and that the settings seem to take effect.
We are using unittest, not pytest...
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I pushed the fixes I made a few days ago. I am not familiar with the work flow on github, and I think it is not exactly intuitive... Am I expected to do something else? I also just 'resolved' the comments you made, which seemed the right thing to do. Please bear with me, I am a noob. :) |
CS lines can now be active high. Ideas taken from
https://github.com/eblot/pyftdi/pull/86/files
Main difference is that we can individually select which CS lines that
shall be active high. This is done using a bitfield.