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verilog/SVA/sequence4 test passes #776

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Oct 18, 2024
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5 changes: 2 additions & 3 deletions regression/verilog/SVA/sequence4.desc
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
KNOWNBUG
CORE
sequence4.sv
--bound 10
^EXIT=10$
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
sequence concatenation is not supported by the BMC engine
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