verilog/SVA/sequence4 test passes

Sequence concatenation is now implemented.
diffblue · Oct 17, 2024 · fe69104 · fe69104
1 parent b72f0c4
commit fe69104
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/regression/verilog/SVA/sequence4.desc b/regression/verilog/SVA/sequence4.desc
@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 sequence4.sv
 --bound 10
 ^EXIT=10$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-sequence concatenation is not supported by the BMC engine