Verilog: add classes, interfaces, packages to parse tree

regression/verilog/class/class1.desc

@@ -1,7 +1,7 @@
 CORE
 class1.sv
---bound 0 --module main
-^no properties$
-^EXIT=10$
+--show-parse
+^Class: myClass$
+^EXIT=0$
 ^SIGNAL=0$
 --

regression/verilog/interface/interface1.desc

@@ -0,0 +1,7 @@
+CORE
+interface1.sv
+--show-parse
+^Interface: myInterface$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/interface/interface1.sv

@@ -0,0 +1,5 @@
+interface myInterface;
+endinterface
+
+module main;
+endmodule

regression/verilog/packages/package1.desc

@@ -1,7 +1,7 @@
 CORE
 package1.sv
---bound 0 --module main
-^no properties$
-^EXIT=10$
+--show-parse
+^Pacakge: my_pkg$
+^EXIT=0$
 ^SIGNAL=0$
 --

src/hw_cbmc_irep_ids.h

@@ -229,8 +229,13 @@ IREP_ID_ONE(specify)
 IREP_ID_ONE(x)
 IREP_ID_ONE(verilog_empty_item)
 IREP_ID_ONE(verilog_import_item)
+IREP_ID_ONE(verilog_interface)
+IREP_ID_ONE(verilog_class)
 IREP_ID_ONE(verilog_module)
+IREP_ID_ONE(verilog_package)
 IREP_ID_ONE(verilog_package_import)
+IREP_ID_ONE(verilog_program)
+IREP_ID_ONE(verilog_udp)
 IREP_ID_ONE(module_source)
 IREP_ID_ONE(module_items)
 IREP_ID_ONE(parameter_port_list)

src/verilog/parser.y

@@ -616,9 +616,13 @@ description:
 	  module_declaration
 		{ PARSER.parse_tree.add_item(stack_expr($1)); }
 	| udp_declaration
+		{ PARSER.parse_tree.add_item(stack_expr($1)); }
 	| interface_declaration
+		{ PARSER.parse_tree.add_item(stack_expr($1)); }
  	| program_declaration
+		{ PARSER.parse_tree.add_item(stack_expr($1)); }
  	| package_declaration
+		{ PARSER.parse_tree.add_item(stack_expr($1)); }
 	| attribute_instance_brace package_item
 		{ add_attributes($2, $1);
 		  PARSER.parse_tree.add_item(stack_expr($2)); }
@@ -713,9 +717,31 @@ module_keyword:
 	;
 
 interface_declaration:
-          TOK_INTERFACE TOK_ENDINTERFACE
+	  interface_nonansi_header
+	  timeunits_declaration_opt
+	  interface_item_brace
+          TOK_ENDINTERFACE
+        	{ $$ = $1; }
         ;
 
+interface_nonansi_header:
+	  attribute_instance_brace
+	  TOK_INTERFACE
+	  lifetime_opt
+	  interface_identifier
+	  	{
+		  init($$, ID_verilog_interface);
+		  stack_expr($$).set(ID_base_name, stack_expr($4).id());
+	  	}
+	  package_import_declaration_brace
+	  parameter_port_list_opt
+	  list_of_ports_opt
+	  ';'
+	  	{
+	  	  $$ = $5;
+	  	}
+	;
+
 program_declaration:
           TOK_PROGRAM TOK_ENDPROGRAM
         ;
@@ -724,32 +750,42 @@ class_declaration:
 	  TOK_CLASS class_identifier
 	  ';'
 		{
-		  $$ = $1;
+		  init($$, ID_verilog_class);
+		  stack_expr($$).set(ID_base_name, stack_expr($2).id());
 	          push_scope(stack_expr($2).id(), "::");
 	        }
 	  class_item_brace
 	  TOK_ENDCLASS
 		{
+		  $$ = $4;
 		  pop_scope();
 	        }
 	;
 
 package_declaration:
           attribute_instance_brace TOK_PACKAGE
+		{ init($$, ID_verilog_package); }
           lifetime_opt
           package_identifier ';'
 		{
-		  $$ = $1;
-	          push_scope(stack_expr($4).id(), "::");
+	          push_scope(stack_expr($5).id(), "::");
 	        }
           timeunits_declaration_opt
           package_item_brace
-          TOK_ENDPACKAGE
+          TOK_ENDPACKAGE endpackage_identifier_opt
 		{
 		  pop_scope();
+		  $$ = $3;
+		  addswap($$, ID_module_items, $9);
+		  stack_expr($$).set(ID_base_name, stack_expr($5).id());
 	        }
         ;
 
+endpackage_identifier_opt:
+	  /* Optional */
+	| TOK_COLON package_identifier
+	;
+
 timeunits_declaration_opt:
 	  /* Optional */
 	;
@@ -939,6 +975,38 @@ config_declaration:
 bind_directive:
           TOK_BIND
         ;
+
+// System Verilog standard 1800-2017
+// A.1.6 Interface items
+
+interface_or_generate_item:
+	  attribute_instance_brace module_common_item
+	| attribute_instance_brace extern_tf_declaration
+	;
+
+extern_tf_declaration:
+	  TOK_EXTERN method_prototype ';'
+	| TOK_EXTERN TOK_FORKJOIN task_prototype ';'
+	;
+
+interface_item_brace:
+	  /* Optional */
+	| interface_item_brace interface_item
+	;
+
+interface_item:
+	  port_declaration ';'
+	| non_port_interface_item
+	;
+
+non_port_interface_item:
+	  generate_region
+	| interface_or_generate_item
+	| program_declaration
+	/* | modport_declaration */
+	| interface_declaration
+	/* | timeunits_declaration */
+	;
 
 // System Verilog standard 1800-2017
 // A.1.9 Class items
@@ -3920,8 +3988,7 @@ genvar_identifier: identifier;
 hierarchical_parameter_identifier: hierarchical_identifier
 	;
 
-interface_identifier:
-	;
+interface_identifier: TOK_NON_TYPE_IDENTIFIER;
 
 module_identifier: TOK_NON_TYPE_IDENTIFIER;
 

src/verilog/verilog_expr.cpp

@@ -63,7 +63,7 @@ void verilog_module_sourcet::show(std::ostream &out) const
   out << '\n';
 }
 
-static void submodules_rec(
+static void dependencies_rec(
   const verilog_module_itemt &module_item,
   std::vector<irep_idt> &dest)
 {
@@ -75,31 +75,91 @@ static void submodules_rec(
   else if(module_item.id() == ID_generate_block)
   {
     for(auto &sub_item : to_verilog_generate_block(module_item).module_items())
-      submodules_rec(sub_item, dest);
+      dependencies_rec(sub_item, dest);
   }
   else if(module_item.id() == ID_generate_if)
   {
     auto &generate_if = to_verilog_generate_if(module_item);
-    submodules_rec(generate_if.then_case(), dest);
+    dependencies_rec(generate_if.then_case(), dest);
     if(generate_if.has_else_case())
-      submodules_rec(generate_if.else_case(), dest);
+      dependencies_rec(generate_if.else_case(), dest);
   }
   else if(module_item.id() == ID_generate_for)
   {
-    submodules_rec(to_verilog_generate_for(module_item).body(), dest);
+    dependencies_rec(to_verilog_generate_for(module_item).body(), dest);
   }
 }
 
-std::vector<irep_idt> verilog_module_sourcet::submodules() const
+std::vector<irep_idt> verilog_item_containert::dependencies() const
 {
   std::vector<irep_idt> result;
 
-  for(auto &item : module_items())
-    submodules_rec(item, result);
+  for(auto &item : items())
+    dependencies_rec(item, result);
 
   return result;
 }
 
+void verilog_packaget::show(std::ostream &out) const
+{
+  out << "Pacakge: " << base_name() << '\n';
+
+  out << "  Items:\n";
+
+  for(auto &item : items())
+    out << "    " << item.pretty() << '\n';
+
+  out << '\n';
+}
+
+void verilog_programt::show(std::ostream &out) const
+{
+  out << "Program: " << base_name() << '\n';
+
+  out << "  Items:\n";
+
+  for(auto &item : items())
+    out << "    " << item.pretty() << '\n';
+
+  out << '\n';
+}
+
+void verilog_classt::show(std::ostream &out) const
+{
+  out << "Class: " << base_name() << '\n';
+
+  out << "  Items:\n";
+
+  for(auto &item : items())
+    out << "    " << item.pretty() << '\n';
+
+  out << '\n';
+}
+
+void verilog_interfacet::show(std::ostream &out) const
+{
+  out << "Interface: " << base_name() << '\n';
+
+  out << "  Items:\n";
+
+  for(auto &item : items())
+    out << "    " << item.pretty() << '\n';
+
+  out << '\n';
+}
+
+void verilog_udpt::show(std::ostream &out) const
+{
+  out << "UDP: " << base_name() << '\n';
+
+  out << "  Items:\n";
+
+  for(auto &item : items())
+    out << "    " << item.pretty() << '\n';
+
+  out << '\n';
+}
+
 static exprt lower(const verilog_non_indexed_part_select_exprt &part_select)
 {
   auto get_width = [](const typet &t) -> mp_integer