Verilog: add packages to parse tree

regression/verilog/packages/package1.desc

@@ -1,7 +1,7 @@
 CORE
 package1.sv
---bound 0 --module main
-^no properties$
+--show-parse
+^Pacakge: my_pkg$
 ^EXIT=10$
 ^SIGNAL=0$
 --

src/hw_cbmc_irep_ids.h

@@ -230,6 +230,7 @@ IREP_ID_ONE(x)
 IREP_ID_ONE(verilog_empty_item)
 IREP_ID_ONE(verilog_import_item)
 IREP_ID_ONE(verilog_module)
+IREP_ID_ONE(verilog_package)
 IREP_ID_ONE(verilog_package_import)
 IREP_ID_ONE(module_source)
 IREP_ID_ONE(module_items)

src/verilog/parser.y

@@ -619,6 +619,7 @@ description:
 	| interface_declaration
  	| program_declaration
  	| package_declaration
+		{ PARSER.parse_tree.add_item(stack_expr($1)); }
 	| attribute_instance_brace package_item
 		{ add_attributes($2, $1);
 		  PARSER.parse_tree.add_item(stack_expr($2)); }
@@ -736,20 +737,28 @@ class_declaration:
 
 package_declaration:
           attribute_instance_brace TOK_PACKAGE
+		{ init($$, ID_verilog_package); }
           lifetime_opt
           package_identifier ';'
 		{
-		  $$ = $1;
-	          push_scope(stack_expr($4).id(), "::");
+	          push_scope(stack_expr($5).id(), "::");
 	        }
           timeunits_declaration_opt
           package_item_brace
-          TOK_ENDPACKAGE
+          TOK_ENDPACKAGE endpackage_identifier_opt
 		{
 		  pop_scope();
+		  $$ = $3;
+		  addswap($$, ID_module_items, $9);
+		  stack_expr($$).set(ID_base_name, stack_expr($5).id());
 	        }
         ;
 
+endpackage_identifier_opt:
+	  /* Optional */
+	| TOK_COLON package_identifier
+	;
+
 timeunits_declaration_opt:
 	  /* Optional */
 	;

src/verilog/verilog_expr.cpp

@@ -100,6 +100,18 @@ std::vector<irep_idt> verilog_module_sourcet::submodules() const
   return result;
 }
 
+void verilog_packaget::show(std::ostream &out) const
+{
+  out << "Pacakge: " << base_name() << '\n';
+
+  out << "  Items:\n";
+
+  for(auto &item : items())
+    out << "    " << item.pretty() << '\n';
+
+  out << '\n';
+}
+
 static exprt lower(const verilog_non_indexed_part_select_exprt &part_select)
 {
   auto get_width = [](const typet &t) -> mp_integer

src/verilog/verilog_expr.h

@@ -2097,6 +2097,59 @@ inline verilog_module_sourcet &to_verilog_module_source(irept &irep)
   return static_cast<verilog_module_sourcet &>(irep);
 }
 
+class verilog_packaget : public irept
+{
+public:
+  explicit verilog_packaget(irep_idt _base_name) : irept(ID_verilog_module)
+  {
+    base_name(_base_name);
+  }
+
+  irep_idt base_name() const
+  {
+    return get(ID_base_name);
+  }
+
+  void base_name(irep_idt base_name)
+  {
+    return set(ID_base_name, base_name);
+  }
+
+  using itemst = std::vector<class verilog_module_itemt>;
+
+  const itemst &items() const
+  {
+    return (const itemst &)(find(ID_module_items).get_sub());
+  }
+
+  itemst &items()
+  {
+    return (itemst &)(add(ID_module_items).get_sub());
+  }
+
+  const source_locationt &source_location() const
+  {
+    return static_cast<const source_locationt &>(find(ID_C_source_location));
+  }
+
+  source_locationt &add_source_location()
+  {
+    return static_cast<source_locationt &>(add(ID_C_source_location));
+  }
+
+  void show(std::ostream &) const;
+};
+
+inline const verilog_packaget &to_verilog_package(const irept &irep)
+{
+  return static_cast<const verilog_packaget &>(irep);
+}
+
+inline verilog_packaget &to_verilog_package(irept &irep)
+{
+  return static_cast<verilog_packaget &>(irep);
+}
+
 class verilog_implicit_typecast_exprt : public unary_exprt
 {
 public:

src/verilog/verilog_parse_tree.cpp

@@ -127,6 +127,8 @@ void verilog_parse_treet::show(const itemt &item, std::ostream &out) const
 {
   if(item.id() == ID_verilog_module)
     to_verilog_module_source(item).show(out);
+  else if(item.id() == ID_verilog_package)
+    to_verilog_package(item).show(out);
   else
     out << item.pretty() << '\n';
 }