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Syntactic checks

Verilog: add classes, interfaces, packages to parse tree #1524

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Verilog: add classes, interfaces, packages to parse tree

Verilog: add classes, interfaces, packages to parse tree #1524

Triggered via pull request October 25, 2024 13:43
@kroeningkroening
synchronize #789
package-to-parse-tree
Status Success
Total duration 1m 31s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
1m 21s
check-clang-format
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