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William #267
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William #267
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# -*- coding: utf-8 -*- | ||
# Copyright (c) 2017 Jason Lowe-Power | ||
# All rights reserved. | ||
# | ||
# Redistribution and use in source and binary forms, with or without | ||
# modification, are permitted provided that the following conditions are | ||
# met: redistributions of source code must retain the above copyright | ||
# notice, this list of conditions and the following disclaimer; | ||
# redistributions in binary form must reproduce the above copyright | ||
# notice, this list of conditions and the following disclaimer in the | ||
# documentation and/or other materials provided with the distribution; | ||
# neither the name of the copyright holders nor the names of its | ||
# contributors may be used to endorse or promote products derived from | ||
# this software without specific prior written permission. | ||
# | ||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
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""" This file creates a barebones system and executes 'hello', a simple Hello | ||
World application. Adds a simple memobj between the CPU and the membus. | ||
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This config file assumes that the x86 ISA was built. | ||
""" | ||
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# import the m5 (gem5) library created when gem5 is built | ||
import m5 | ||
# import all of the SimObjects | ||
from m5.objects import * | ||
from m5.util.convert import * | ||
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import math | ||
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# create the system we are going to simulate | ||
system = System() | ||
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# Set the clock fequency of the system (and all of its children) | ||
system.clk_domain = SrcClockDomain() | ||
system.clk_domain.clock = '1GHz' | ||
system.clk_domain.voltage_domain = VoltageDomain() | ||
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# Set up the system | ||
system.mem_mode = 'timing' # Use timing accesses AddrRange('1023MB', '1047556KiB')] | ||
system.mem_ranges = [AddrRange(0, '255MB'), AddrRange('255MB', '256MB')] # Create an address range | ||
# system.mem_ranges = [AddrRange(0, '1023MB'), AddrRange('1023MB', '1024MB')] # Create an address range | ||
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# system.mem_ranges = [AddrRange(0, '1MB'), AddrRange('1MB', '1024MB')] # Create an address range | ||
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addr_range = system.mem_ranges[0] | ||
queue_ranges = [system.mem_ranges[1]] | ||
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system.membus = SystemXBar(width = 64, max_routing_table_size = 16777216) | ||
# system.membus = IOXBar(width = 64) | ||
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# Below here marks with CPU | ||
system.cpu = TimingSimpleCPU() | ||
system.cpu.icache_port = system.membus.cpu_side_ports #system.cpu.icache.cpu_side | ||
system.cpu.dcache_port = system.membus.cpu_side_ports #system.queue_dcache_xbar.cpu_side_ports | ||
# create the interrupt controller for the CPU and connect to the membus | ||
system.cpu.createInterruptController() | ||
system.cpu.interrupts[0].pio = system.membus.mem_side_ports | ||
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports | ||
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports | ||
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system.msg_queue = MessageQueue(my_range=queue_ranges[0], queueSize=18) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Shouldn't you have a message queue per core? |
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system.msg_queue.cpu_side = system.membus.mem_side_ports | ||
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mem_ctrls = [] | ||
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num_chnls = 1 | ||
intlv_bits = int(math.log(num_chnls, 2)) | ||
cache_line_size = 64 | ||
intlv_low_bit = int(math.log(cache_line_size, 2)) | ||
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for chnl in range(num_chnls): | ||
# size = addr_range.size() | ||
interface = HBM_1000_4H_1x128() | ||
interface.range = AddrRange(addr_range.start, size = addr_range.size(), | ||
intlvHighBit = intlv_low_bit + intlv_bits - 1, | ||
xorHighBit = 0, | ||
intlvBits = intlv_bits, | ||
intlvMatch = chnl) | ||
ctrl = MemCtrl() | ||
ctrl.dram = interface | ||
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#ctrl.dram.null = True | ||
#ctrl.dram.addr_mapping = addr_map | ||
#ctrl.dram.page_policy = page_policy | ||
mem_ctrls.append(ctrl) | ||
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. You should simplify this for now. You should simply have one memory channel. |
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my_ctrl = MemCtrl() # this memory controller doesnt actually get used, is only used to trick the CPU into adding the AddrRange as a valid AddrRange | ||
my_ctrl.dram = DDR3_1600_8x8() | ||
my_ctrl.dram.range = queue_ranges[0] #system.mem_ranges[1] | ||
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mem_ctrls.append(my_ctrl) | ||
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system.mem_ctrls = mem_ctrls | ||
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# for mem_ctrl in system.mem_ctrls: | ||
# mem_ctrl.port = system.membus.mem_side_ports | ||
system.mem_ctrls[0].port = system.membus.mem_side_ports | ||
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system.mem_ctrls[1].port = system.msg_queue.mem_side # connecting fake memory to msg queue | ||
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# # Connect the system up to the membus | ||
system.system_port = system.membus.cpu_side_ports | ||
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# below here also for cpu | ||
process = Process() | ||
# process.map(vaddr=0x1000000, paddr=0x3CF9BDC0, size=4096, cacheable=False) | ||
# Set the command | ||
# grab the specific path to the binary | ||
thispath = os.path.dirname(os.path.realpath(__file__)) | ||
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binpath = os.path.join(thispath, '../../', | ||
'tests/test-progs/hello/bin/x86/linux/mapped_queue_fixed_private') | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This doesn't have to be in test-progs, and you should avoid checking in binaries. |
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# binpath = os.path.join(thispath, '../../', | ||
# 'tests/test-progs/hello/bin/x86/linux/no_tuple') | ||
# cmd is a list which begins with the executable (like argv) | ||
process.cmd = [binpath] | ||
# Set the cpu to use the process as its workload and create thread contexts | ||
system.cpu.workload = process | ||
# system.cpu.workload.map(vaddr=0x1000000, paddr=0x3CF9BDC0, size=4096) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This |
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system.cpu.createThreads() | ||
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system.workload = SEWorkload.init_compatible(binpath) | ||
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# set up the root SimObject and start the simulation | ||
root = Root(full_system = False, system = system) | ||
# instantiate all of the objects we've created above | ||
m5.instantiate() | ||
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# process.map(vaddr=0x10000, paddr=0x3CF9BDC0, size=4096, cacheable=False) | ||
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process.map(vaddr=0x1000000, paddr=0xFF00000, size=4096, cacheable=True) | ||
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print("Beginning simulation!") | ||
exit_event = m5.simulate() | ||
print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Don't use Another link: https://www.geeksforgeeks.org/formatted-string-literals-f-strings-python/# |
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# Copyright (c) 2015 Jason Power | ||
# All rights reserved. | ||
# | ||
# Redistribution and use in source and binary forms, with or without | ||
# modification, are permitted provided that the following conditions are | ||
# met: redistributions of source code must retain the above copyright | ||
# notice, this list of conditions and the following disclaimer; | ||
# redistributions in binary form must reproduce the above copyright | ||
# notice, this list of conditions and the following disclaimer in the | ||
# documentation and/or other materials provided with the distribution; | ||
# neither the name of the copyright holders nor the names of its | ||
# contributors may be used to endorse or promote products derived from | ||
# this software without specific prior written permission. | ||
# | ||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
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""" | ||
This is the RISCV equivalent to `simple.py` (which is designed to run using the | ||
X86 ISA). More detailed documentation can be found in `simple.py`. | ||
""" | ||
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import m5 | ||
from m5.objects import * | ||
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num_cores = 4 | ||
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system = System() | ||
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system.clk_domain = SrcClockDomain() | ||
system.clk_domain.clock = "1GHz" | ||
system.clk_domain.voltage_domain = VoltageDomain() | ||
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system.mem_mode = "timing" | ||
system.mem_ranges = [AddrRange("512MB")] | ||
system.cpu = RiscvTimingSimpleCPU(num_cores=num_cores) | ||
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system.membus = SystemXBar() | ||
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system.cpu.icache_port = system.membus.cpu_side_ports | ||
system.cpu.dcache_port = system.membus.cpu_side_ports | ||
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system.cpu.createInterruptController() | ||
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system.mem_ctrl = MemCtrl() | ||
system.mem_ctrl.dram = DDR3_1600_8x8() | ||
system.mem_ctrl.dram.range = system.mem_ranges[0] | ||
system.mem_ctrl.port = system.membus.mem_side_ports | ||
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system.system_port = system.membus.cpu_side_ports | ||
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thispath = os.path.dirname(os.path.realpath(__file__)) | ||
binary = os.path.join( | ||
thispath, | ||
"../../../", | ||
"tests/test-progs/hello/bin/riscv/linux/hello", | ||
) | ||
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system.workload = SEWorkload.init_compatible(binary) | ||
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process = Process() | ||
process.cmd = [binary] | ||
system.cpu.workload = process | ||
system.cpu.createThreads() | ||
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root = Root(full_system=False, system=system) | ||
m5.instantiate() | ||
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print("Beginning simulation!") | ||
exit_event = m5.simulate() | ||
print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause())) |
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# -*- coding: utf-8 -*- | ||
# Copyright (c) 2015 Jason Power | ||
# All rights reserved. | ||
# | ||
# Redistribution and use in source and binary forms, with or without | ||
# modification, are permitted provided that the following conditions are | ||
# met: redistributions of source code must retain the above copyright | ||
# notice, this list of conditions and the following disclaimer; | ||
# redistributions in binary form must reproduce the above copyright | ||
# notice, this list of conditions and the following disclaimer in the | ||
# documentation and/or other materials provided with the distribution; | ||
# neither the name of the copyright holders nor the names of its | ||
# contributors may be used to endorse or promote products derived from | ||
# this software without specific prior written permission. | ||
# | ||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
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""" Caches with options for a simple gem5 configuration script | ||
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This file contains L1 I/D and L2 caches to be used in the simple | ||
gem5 configuration script. It uses the SimpleOpts wrapper to set up command | ||
line options from each individual class. | ||
""" | ||
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import m5 | ||
from m5.objects import Cache | ||
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# Some specific options for caches | ||
# For all options see src/mem/cache/BaseCache.py | ||
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class L1Cache(Cache): | ||
"""Simple L1 Cache with default values""" | ||
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assoc = 2 | ||
tag_latency = 2 | ||
data_latency = 2 | ||
response_latency = 2 | ||
mshrs = 4 | ||
tgts_per_mshr = 20 | ||
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def __init__(self, options=None): | ||
super(L1Cache, self).__init__() | ||
pass | ||
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def connectBus(self, bus): | ||
"""Connect this cache to a memory-side bus""" | ||
self.mem_side = bus.cpu_side_ports | ||
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def connectCPU(self, cpu): | ||
"""Connect this cache's port to a CPU-side port | ||
This must be defined in a subclass""" | ||
raise NotImplementedError | ||
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class L1ICache(L1Cache): | ||
"""Simple L1 instruction cache with default values""" | ||
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# Set the default size | ||
size = "16kB" | ||
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def __init__(self, opts=None): | ||
super(L1ICache, self).__init__(opts) | ||
if not opts or not opts.l1i_size: | ||
return | ||
self.size = opts.l1i_size | ||
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def connectCPU(self, cpu): | ||
"""Connect this cache's port to a CPU icache port""" | ||
self.cpu_side = cpu.icache_port | ||
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class L1DCache(L1Cache): | ||
"""Simple L1 data cache with default values""" | ||
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# Set the default size | ||
size = "32kB" | ||
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def __init__(self, opts=None): | ||
super(L1DCache, self).__init__(opts) | ||
if not opts or not opts.l1d_size: | ||
return | ||
self.size = opts.l1d_size | ||
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def connectCPU(self, cpu): | ||
"""Connect this cache's port to a CPU dcache port""" | ||
self.cpu_side = cpu.dcache_port | ||
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class L2Cache(Cache): | ||
"""Simple L2 Cache with default values""" | ||
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# Default parameters | ||
size = "256kB" | ||
assoc = 8 | ||
tag_latency = 20 | ||
data_latency = 20 | ||
response_latency = 20 | ||
mshrs = 20 | ||
tgts_per_mshr = 12 | ||
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def __init__(self, opts=None): | ||
super(L2Cache, self).__init__() | ||
if not opts or not opts.l2_size: | ||
return | ||
self.size = opts.l2_size | ||
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def connectCPUSideBus(self, bus): | ||
self.cpu_side = bus.mem_side_ports | ||
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def connectMemSideBus(self, bus): | ||
self.mem_side = bus.cpu_side_ports |
There was a problem hiding this comment.
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The reason will be displayed to describe this comment to others. Learn more.
The system's address range should just be 0-256MiB (or whatever the SYSTEM'S address range is).
Then, you should set a different address range for the message queue.