Tag prob real implementation

configs-npb-gapbs/restore_both.py

@@ -185,7 +185,7 @@ def run():
     for interval_number in range(100):
         print("Interval number: {}".format(interval_number))
         exit_event = m5.simulate(10_000_000_000)  # 10 ms
-        # m5.stats.dump()
+        #m5.stats.dump()
 
         if exit_event.getCause() != "simulate() limit reached":
             if (

src/cpu/testers/dr_trace_player/trace_player.cc

@@ -86,7 +86,6 @@ DRTracePlayer::tryExecuteInst(DRTraceReader::TraceRef &cur_ref)
         // End of trace for this player exit the simulation
         // TODO: Move this to when the last instruction is completed
         exitSimLoopNow("End of DRTrace");
-        return;
     }
 
     DPRINTF(DRTrace, "Exec reference pc: %0#x, addr: %0#x, size: %d, "

src/cpu/testers/dr_trace_player/trace_reader.cc

@@ -171,10 +171,6 @@ DRTraceReader::getNextTraceReference(unsigned player_id)
         case TRACE_TYPE_PREFETCHT1:
         case TRACE_TYPE_PREFETCHT2:
         case TRACE_TYPE_PREFETCHNTA:
-            if (raw_entry.addr == 0) {
-                warn("Encountered a prefetch req with Addr = 0 \n");
-                return getNextTraceReference(player_id);
-	     }
             ref.addr = raw_entry.addr;
             ref.size = raw_entry.size;
             ref.isValid = true;

src/mem/DRAMInterface.py

@@ -187,13 +187,13 @@ class DRAMInterface(MemInterface):
     tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
 
     tTAGBURST = Param.Latency("0ns", "tRL_FAST")
-    tRLFAST   = Param.Latency("0ns", "tRL_FAST")
+    tRL_FAST   = Param.Latency("0ns", "tRL_FAST")
     tHM2DQ    = Param.Latency("0ns", "tHM2DQ")
     tRTW_int  = Param.Latency("0ns", "tRTW_int")
     tRFBD     = Param.Latency("0ns", "tRFBD")
     tRCD_FAST = Param.Latency("0ns", "tRCD_FAST")
+    tRC_FAST  = Param.Latency("0ns", "tRCD_FAST")
     flushBuffer_high_thresh_perc = Param.Percent(0, "Threshold to force writes")
-    flush_buffer_size = Param.Unsigned(0, "flush buffer size")
 
     # number of data beats per clock. with DDR, default is 2, one per edge
     # used in drampower.cc
@@ -1304,11 +1304,12 @@ class TDRAM(DRAMInterface):
 
     # new
     tTAGBURST = "1ns"
-    tRLFAST = "1ns"
+    tRL_FAST = "1ns"
     tHM2DQ = "1ns"
     tRTW_int = "2ns"
     tRFBD = "2ns"
     tRCD_FAST = "7.5ns"
+    tRC_FAST = "10.5ns"
     enable_read_flush_buffer = True
     flushBuffer_high_thresh_perc = 80
 
@@ -1390,14 +1391,13 @@ class TDRAM_32(DRAMInterface):
 
     # new
     tTAGBURST = "0.5ns"
-    tRLFAST = "7.5ns"
+    tRL_FAST = "7.5ns"
     tHM2DQ = "0ns"
     tRTW_int = "1ns"
     tRFBD = "1ns"
     tRCD_FAST = "7.5ns"
     enable_read_flush_buffer = True
     flushBuffer_high_thresh_perc = 80
-    flush_buffer_size = 32
 
     tRP = "14ns"
 

src/mem/PolicyManager.py

@@ -5,7 +5,7 @@
 from m5.objects.AbstractMemory import AbstractMemory
 from m5.objects.DRAMInterface import *
 
-class Policy(Enum): vals = ['CascadeLakeNoPartWrs', 'Oracle', 'BearWriteOpt', 'Rambus']
+class Policy(Enum): vals = ['CascadeLakeNoPartWrs', 'Oracle', 'BearWriteOpt', 'Rambus', 'RambusTagProbOpt']
 class ReplPolicySetAssoc(Enum): vals = ['bip_rp', 'brrip_rp', 'dueling_rp', 'fifo_rp', 'lfu_rp', 'lru_rp', 'mru_rp', 'random_rp', 'second_chance_rp', 'ship_rp', 'tree_plru_rp', 'weighted_lru_rp']
 
 class PolicyManager(AbstractMemory):

src/mem/abstract_mem.hh

@@ -46,6 +46,7 @@
 #ifndef __MEM_ABSTRACT_MEMORY_HH__
 #define __MEM_ABSTRACT_MEMORY_HH__
 
+#include "enums/Policy.hh"
 #include "mem/backdoor.hh"
 #include "mem/port.hh"
 #include "params/AbstractMemory.hh"
@@ -225,6 +226,8 @@ class AbstractMemory : public ClockedObject
 
     void initState() override;
 
+    enums::Policy locMemPolicy;
+
     virtual Tick get_tRP() { panic("AbstractMemory get_tRP should not be executed from here.\n");
                              return false;}
     virtual Tick get_tRCD_RD() { panic("AbstractMemory get_tRCD_RD should not be executed from here.\n");

src/mem/dram_interface.cc

@@ -48,6 +48,7 @@
 #include "debug/DRAMPower.hh"
 #include "debug/DRAMState.hh"
 #include "debug/MemCtrl.hh"
+#include "enums/Policy.hh"
 #include "sim/system.hh"
 
 namespace gem5
@@ -61,7 +62,6 @@ namespace memory
 std::pair<MemPacketQueue::iterator, Tick>
 DRAMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
 {
-    DPRINTF(DRAM, "in dram->chooseNextFRFCFS func\n");
     std::vector<uint32_t> earliest_banks(ranksPerChannel, 0);
 
     // Has minBankPrep been called to populate earliest_banks?
@@ -365,6 +365,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
     Tick act_at = MaxTick;
     // get the rank
     Rank& rank_ref = *ranks[mem_pkt->rank];
+
     assert(rank_ref.inRefIdleState());
 
     // are we in or transitioning to a low-power state and have not scheduled
@@ -394,20 +395,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         }
 
         // next we need to account for the delay in activating the page
-        Tick act_tick;
-        if (mem_pkt->isLocMem) {
-            if (polMan->locMemPolicy == enums::RambusTagProbOpt) {
-                act_tick = std::max(std::max(bank_ref.tagActAllowedAt, bank_ref.actAllowedAt), curTick());
-
-                if (bank_ref.tagActAllowedAt > bank_ref.actAllowedAt && bank_ref.tagActAllowedAt > curTick()) {
-                    stats.actDelayedDueToTagAct++;
-                }
-            } else {
-                act_tick = std::max(bank_ref.actAllowedAt, curTick());
-            }
-        } else {
-            act_tick = std::max(bank_ref.actAllowedAt, curTick());
-        }
+        Tick act_tick = std::max(bank_ref.actAllowedAt, curTick());
 
         // Record the activation and deal with all the global timing
         // constraints caused be a new activation (tRRD and tXAW)
@@ -449,18 +437,21 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         }
     }
 
-    DPRINTF(DRAM, "Schedule RD/WR burst at tick %d\n", cmd_at);
+        DPRINTF(DRAM, "Schedule RD/WR burst at tick %d\n", cmd_at);
 
     // update the packet ready time
     Tick stall_delay = 0;
     if(mem_pkt->isTagCheck) {
-        assert(mem_pkt->isLocMem);
 
+        assert(mem_pkt->isLocMem);
+
         // Calculating the tag check ready time
         if (mem_pkt->pkt->owIsRead) {
-            mem_pkt->tagCheckReady = cmd_at - tRCD_RD + tRCD_FAST + tRLFAST;
+            assert((cmd_at + tRCD_FAST + tRL_FAST) > tRCD_RD);
+            mem_pkt->tagCheckReady = (cmd_at + tRCD_FAST + tRL_FAST) - tRCD_RD;
         } else {
-            mem_pkt->tagCheckReady = cmd_at - tRCD_RD - tRTW_int + tRCD_FAST + tRLFAST;
+            assert((cmd_at + tRCD_FAST + tRL_FAST) > (tRCD_RD + tRTW_int));
+            mem_pkt->tagCheckReady = (cmd_at + tRCD_FAST + tRL_FAST) - (tRCD_RD + tRTW_int);
         }
         stats.tagResBursts++;
 
@@ -470,15 +461,10 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
             stats.tagBursts++;
         }
 
-        if (polMan->locMemPolicy == enums::RambusTagProbOpt) {
-            assert((mem_pkt->tagCheckReady + tRC_FAST) > (tRL_FAST + tRCD_FAST));
-            bank_ref.tagActAllowedAt = (mem_pkt->tagCheckReady + tRC_FAST) - (tRL_FAST + tRCD_FAST);
-        }
-
         // Calculating the data ready time
         if (mem_pkt->pkt->owIsRead) {
 
-            mem_pkt->readyTime = cmd_at + std::max(tRL, tRLFAST + tHM2DQ) + tBURST;
+            mem_pkt->readyTime = cmd_at + std::max(tRL,  tRL_FAST + tHM2DQ) + tBURST;
 
             // Rd Miss Clean
             if (mem_pkt->pkt->owIsRead && !mem_pkt->pkt->isHit && !mem_pkt->pkt->isDirty) {
@@ -566,7 +552,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
 
                 tempFlushBuffer.push_back(std::make_pair(pushBackFBTick, mem_pkt->pkt->dirtyLineAddr));
 
-                if ((tempFlushBuffer.size() + flushBuffer.size()) >= (flushBufferSize * flushBufferHighThreshold) &&
+                if ((tempFlushBuffer.size() + flushBuffer.size()) >= (banksPerRank * flushBufferHighThreshold) &&
                      !readFlushBufferEvent.scheduled() &&
                      !flushBuffer.empty()) {
 
@@ -620,17 +606,9 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         }
 
     } else {
-        // assert(mem_pkt->tagCheckReady == MaxTick);
+        assert(mem_pkt->tagCheckReady == MaxTick);
         if (mem_pkt->isRead()) {
             mem_pkt->readyTime = cmd_at + tRL + tBURST;
-            if (mem_pkt->isLocMem) {
-                if(polMan->locMemPolicy == enums::RambusTagProbOpt &&
-                   !mem_pkt->pkt->isHit &&
-                   mem_pkt->pkt->isDirty) {
-                    // a probed Rd Miss Dirty
-                    mem_pkt->pkt->hasDirtyData = true;
-                }
-            }
         } else {
             mem_pkt->readyTime = cmd_at + tWL + tBURST;
         }
@@ -651,8 +629,9 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         }
     }
 
+
     DPRINTF(DRAMT, "curr pkt, addr: %d, isRd: %d, isTC: %d, bank %d, row %d, act: %d, RdAlw: %d, WrAlw: %d, cmd: %d, rdy: %d\n", 
-    mem_pkt->getAddr(), mem_pkt->isRead(), mem_pkt->isTagCheck, (unsigned) mem_pkt->bank, (unsigned) mem_pkt->row,
+    mem_pkt->addr, mem_pkt->pkt->isRead(), mem_pkt->pkt->isTagCheck, (unsigned) mem_pkt->bank, (unsigned) mem_pkt->row,
     act_at/1000, bank_ref.rdAllowedAt/1000, bank_ref.wrAllowedAt/1000, cmd_at/1000, mem_pkt->readyTime/1000);
 
     rank_ref.lastBurstTick = cmd_at;
@@ -853,15 +832,6 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
     return std::make_pair(cmd_at, cmd_at + burst_gap);
 }
 
-void
-DRAMInterface::updateTagActAllowed(unsigned rankNumber, unsigned bankNumber, Tick BSlotTagBankBusyAt) 
-{
-    assert(BSlotTagBankBusyAt!=MaxTick);
-    ranks[rankNumber]->banks[bankNumber].tagActAllowedAt = BSlotTagBankBusyAt;
-    DPRINTF(DRAM, "updateTagFunc tagActAllowedAt change, rank/bank %d/%d -- tagActAllowedAt: %d\n",
-        rankNumber, bankNumber, BSlotTagBankBusyAt);
-}
-
 void
 DRAMInterface::addRankToRankDelay(Tick cmd_at)
 {
@@ -892,10 +862,10 @@ DRAMInterface::DRAMInterface(const DRAMInterfaceParams &_p)
       tRFC(_p.tRFC), tREFI(_p.tREFI), tRRD(_p.tRRD), tRRD_L(_p.tRRD_L),
       tPPD(_p.tPPD), tAAD(_p.tAAD),
       tXAW(_p.tXAW), tXP(_p.tXP), tXS(_p.tXS),
-      tTAGBURST(_p.tTAGBURST), tRLFAST(_p.tRLFAST), tHM2DQ(_p.tHM2DQ),
+      tTAGBURST(_p.tTAGBURST),  tRL_FAST(_p. tRL_FAST), tHM2DQ(_p.tHM2DQ),
       tRTW_int(_p.tRTW_int), tRFBD(_p.tRFBD), tRCD_FAST(_p.tRCD_FAST),
+      tRC_FAST(_p.tRC_FAST),
       flushBufferHighThreshold(_p.flushBuffer_high_thresh_perc / 100.0),
-      flushBufferSize(_p.flush_buffer_size),
       clkResyncDelay(_p.tBURST_MAX),
       dataClockSync(_p.data_clock_sync),
       burstInterleave(tBURST != tBURST_MIN),
@@ -2278,6 +2248,8 @@ DRAMInterface::DRAMStats::DRAMStats(DRAMInterface &_dram)
              "Maximum flush buffer length when enqueuing"),
     ADD_STAT(refSchdRFB, statistics::units::Count::get(),
              "Maximum flush buffer length when enqueuing"),
+    ADD_STAT( actDelayedDueToTagAct, statistics::units::Count::get(),
+             " "),
     ADD_STAT(perBankRdBursts, statistics::units::Count::get(),
              "Per bank write bursts"),
     ADD_STAT(perBankWrBursts, statistics::units::Count::get(),

src/mem/dram_interface.hh

@@ -509,13 +509,13 @@ class DRAMInterface : public MemInterface
     const Tick tXP;
     const Tick tXS;
     const Tick tTAGBURST;
-    const Tick tRLFAST;
+    const Tick tRL_FAST;
     const Tick tHM2DQ;
     const Tick tRTW_int;
     const Tick tRFBD;
     const Tick tRCD_FAST;
+    const Tick tRC_FAST;
     float flushBufferHighThreshold;
-    unsigned flushBufferSize;
     const Tick clkResyncDelay;
     const bool dataClockSync;
     const bool burstInterleave;
@@ -602,6 +602,7 @@ class DRAMInterface : public MemInterface
         statistics::Scalar totPktsPushedFB;
         statistics::Scalar maxFBLenEnq;
         statistics::Scalar refSchdRFB;
+        statistics::Scalar actDelayedDueToTagAct;
 
         /** DRAM per bank stats */
         statistics::Vector perBankRdBursts;
@@ -871,7 +872,7 @@ class DRAMInterface : public MemInterface
     Tick getTRCDFAST() override { return tRCD_FAST;}
 
     void updateTagActAllowed(unsigned rankNumber, unsigned bankNumber, Tick BSlotTagBankBusyAt) override;
-
+    
     DRAMInterface(const DRAMInterfaceParams &_p);
 };