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fix bugs and get working scheduling
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UnsignedByte committed Oct 17, 2024
1 parent f240c56 commit 3fc941e
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Showing 6 changed files with 80 additions and 8 deletions.
1 change: 0 additions & 1 deletion crates/filament/src/ir_passes/lower/utils.rs
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,6 @@ impl NameGenerator {

/// Returns the name of an [ir::Param].
pub fn param_name(&self, idx: ParamIdx, comp: &Component) -> String {
println!("Getting param name for {}", comp.display(idx));
comp.src_info
.as_ref()
.map(|src| src.params.get(idx).to_string())
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11 changes: 9 additions & 2 deletions crates/filament/src/ir_passes/schedule/retime.rs
Original file line number Diff line number Diff line change
Expand Up @@ -77,9 +77,15 @@ impl Retime {
rhs: live,
});
// Set up ports to the component

// clk and reset ports are unannotated
comp.unannotated_ports =
Box::new(vec![("clk".into(), 1), ("reset".into(), 1)]);

// input port
let input = ir::Port {
owner: ir::PortOwner::Sig {
dir: ir::Direction::In,
dir: ir::Direction::Out,
},
width,
live: ir::Liveness {
Expand Down Expand Up @@ -110,9 +116,10 @@ impl Retime {
comp.get_mut(input).live.idxs.push(input_param);
src_info.ports.push(input, "in".into());

// output port
let output = ir::Port {
owner: ir::PortOwner::Sig {
dir: ir::Direction::Out,
dir: ir::Direction::In,
},
width,
live: ir::Liveness {
Expand Down
19 changes: 14 additions & 5 deletions crates/filament/src/ir_passes/schedule/solve.rs
Original file line number Diff line number Diff line change
Expand Up @@ -264,7 +264,7 @@ impl Visitor for Solve {
}

let model = self.sol.get_model().unwrap();
println!("Model: {}", self.sol.display(model));
log::trace!("Model solution: {}", self.sol.display(model));

let SExprData::List(bindings) = self.sol.get(model) else {
unreachable!(
Expand Down Expand Up @@ -332,15 +332,19 @@ impl Visitor for Solve {

let time = *bindings.get(s).unwrap();

println!("Invocation {} is scheduled at time {}", inv_idx, time);

let time = data.comp.add(ir::Expr::Concrete(time));

let time = data.comp.add(ir::Time {
event,
offset: time,
});

log::debug!(
"Invocation {} scheduled at cycle {}",
data.comp.display(inv_idx),
data.comp.display(time)
);

// Set the time of the invocation
let inv = data.comp.get_mut(inv_idx);

Expand Down Expand Up @@ -378,8 +382,6 @@ impl Visitor for Solve {

let end = *bindings.get(s).unwrap();

println!("Port {} is live from {} to {}", pidx, start, end);

let start = data.comp.add(ir::Expr::Concrete(start));
let end = data.comp.add(ir::Expr::Concrete(end));

Expand All @@ -390,6 +392,13 @@ impl Visitor for Solve {

let end = data.comp.add(ir::Time { event, offset: end });

log::debug!(
"Port {} scheduled to be live from [{}, {}]",
data.comp.display(pidx),
data.comp.display(start),
data.comp.display(end)
);

let port = data.comp.get_mut(pidx);

port.live.range = ir::Range { start, end };
Expand Down
1 change: 1 addition & 0 deletions tests/run/schedule.expect
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
{"out0": {"0": [25], "1": [5], "2": [11]}, "out1": {"0": [25], "1": [5], "2": [11]}, "cycles": 13}
44 changes: 44 additions & 0 deletions tests/run/schedule.fil
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
import "primitives/core.fil";

comp DelayedAdd[W, D]<'G: 1>(
in0: ['G, 'G+1] W,
in1: ['G, 'G+1] W,
) -> (
out: ['G+D, 'G+D+1] W
) where W > 0
{
sum := new Add[W]<'G>(in0, in1);

delayed := new Shift[W, D]<'G>(sum.out);

out = delayed.out;
}

comp DelayedDup[W, D]<'G: 1>(
in: ['G, 'G+1] W,
) -> (
out0: ['G+D, 'G+D+1] W,
out1: ['G+D, 'G+D+1] W
) where W > 0
{
delayed := new Shift[W, D]<'G>(in);

out0 = delayed.out;
out1 = delayed.out;
}

#[toplevel, schedule]
comp main<'G: 1>(
go: interface['G],
in0: ['G, 'G+1] 32,
in1: ['G, 'G+1] 32,
) -> (
out0: ['G+10, 'G+11] 32,
out1: ['G+10, 'G+11] 32
)
{
sum := new DelayedAdd[32, 1]<'G>(in0, in1);
dup := new DelayedDup[32, 1]<'G>(sum.out);
out0 = dup.out0;
out1 = dup.out1;
}
12 changes: 12 additions & 0 deletions tests/run/schedule.fil.data
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
{
"in0": [
10,
2,
5
],
"in1": [
15,
3,
6
]
}

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