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`ifndef PROJECT_CROSSBAR_V | ||
`define PROJECT_CROSSBAR_V | ||
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//Crossbar in Verilog | ||
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module crossbars_BlockingWithOverride #( | ||
parameter int BIT_WIDTH = 32, | ||
parameter int N_INPUTS = 2, | ||
parameter int N_OUTPUTS = 2, | ||
localparam int CONTROL_BIT_WIDTH = $clog2(N_INPUTS * N_OUTPUTS) | ||
) ( | ||
input logic [BIT_WIDTH - 1:0] recv_msg[N_INPUTS], | ||
input logic recv_val[N_INPUTS], | ||
output logic recv_rdy[N_INPUTS], | ||
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output logic [BIT_WIDTH - 1:0] send_msg[N_OUTPUTS], | ||
output logic send_val[N_OUTPUTS], | ||
input logic send_rdy[N_OUTPUTS], | ||
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input logic input_override, | ||
input logic output_override, | ||
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input logic reset, | ||
input logic clk, | ||
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input logic [CONTROL_BIT_WIDTH - 1:0] control, | ||
input logic control_val, | ||
output logic control_rdy | ||
); | ||
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logic [CONTROL_BIT_WIDTH - 1:0] stored_control; | ||
logic [$clog2(N_INPUTS) - 1:0] input_sel; | ||
logic [$clog2(N_OUTPUTS) - 1:0] output_sel; | ||
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always_ff @(posedge clk) begin | ||
if (reset) begin | ||
stored_control <= 0; | ||
end else if (control_val) begin | ||
stored_control <= control; | ||
end else begin | ||
stored_control <= stored_control; | ||
end | ||
end | ||
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assign control_rdy = 1; | ||
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assign input_sel = stored_control[CONTROL_BIT_WIDTH-1:CONTROL_BIT_WIDTH-$clog2(N_INPUTS)]; | ||
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assign output_sel = stored_control[CONTROL_BIT_WIDTH-$clog2( | ||
N_INPUTS | ||
)-1 : CONTROL_BIT_WIDTH-$clog2( | ||
N_INPUTS | ||
)-$clog2( | ||
N_OUTPUTS | ||
)]; | ||
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always_comb begin | ||
for (int i = 0; i < N_OUTPUTS; i = i + 1) begin | ||
/* verilator lint_off WIDTH */ | ||
if ((i != output_sel)) begin | ||
/* verilator lint_on WIDTH */ | ||
send_msg[i] = 0; | ||
send_val[i] = 0; | ||
end else begin | ||
send_msg[i] = recv_msg[input_sel]; | ||
send_val[i] = recv_val[input_sel]; | ||
end | ||
end | ||
for (int i = 0; i < N_INPUTS; i = i + 1) begin | ||
/* verilator lint_off WIDTH */ | ||
if ((i != input_sel)) begin | ||
/* verilator lint_on WIDTH */ | ||
recv_rdy[i] = 0; | ||
end else begin | ||
recv_rdy[i] = send_rdy[output_sel]; | ||
end | ||
end | ||
end | ||
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endmodule | ||
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`endif |