Add Nexys A7 support for SPI Flash

chipsalliance · Jan 9, 2020 · d4d0c5d · d4d0c5d
1 parent 9b22a00
commit d4d0c5d
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Showing 3 changed files with 56 additions and 5 deletions.
diff --git a/data/swervolf_nexys.xdc b/data/swervolf_nexys.xdc
@@ -22,3 +22,9 @@ set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports i_uart_r
 set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports o_uart_tx]
 
 set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw0 }];
+
+set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports o_flash_mosi]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports i_flash_miso]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports o_flash_cs_n];
diff --git a/data/swervolf_nexys_write_flash.cfg b/data/swervolf_nexys_write_flash.cfg
@@ -0,0 +1,24 @@
+interface ftdi
+ftdi_device_desc "Digilent USB Device"
+ftdi_vid_pid 0x0403 0x6010
+ftdi_channel 0
+ftdi_layout_init 0x0088 0x008b
+reset_config none
+adapter_khz 10000
+
+transport select jtag
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+
+if { [info exists BINFILE] } {
+	set _BINFILE $BINFILE
+} else {
+	set _BINFILE boot.bin
+}
+
+init
+jtagspi_init 0 bscan_spi_xc7a100t.bit
+jtagspi_program $_BINFILE 0x0
+shutdown
+
diff --git a/rtl/swervolf_nexys.v b/rtl/swervolf_nexys.v
@@ -23,7 +23,7 @@
 
 `default_nettype none
 module swervolf_nexys_a7
-  #(parameter bootrom_file = "blinky.vh")
+  #(parameter bootrom_file = "spi_uimage_loader.vh")
    (input wire 	       clk,
     input wire 	       rstn,
     output wire [12:0] ddram_a,
@@ -41,6 +41,9 @@ module swervolf_nexys_a7
     output wire        ddram_cke,
     output wire        ddram_odt,
     input wire 	       sw0,
+    output wire        o_flash_cs_n,
+    output wire        o_flash_mosi,
+    input wire 	       i_flash_miso,
     input wire 	       i_uart_rx,
     output wire        o_uart_tx,
     output reg         led0);
@@ -156,6 +159,24 @@ module swervolf_nexys_a7
    wire [31:0] dmi_reg_rdata;
    wire        dmi_hard_reset;
 
+   wire        flash_sclk;
+
+   STARTUPE2 STARTUPE2
+     (
+      .CFGCLK    (),
+      .CFGMCLK   (),
+      .EOS       (),
+      .PREQ      (),
+      .CLK       (1'b0),
+      .GSR       (1'b0),
+      .GTS       (1'b0),
+      .KEYCLEARB (1'b1),
+      .PACK      (1'b0),
+      .USRCCLKO  (flash_sclk),
+      .USRCCLKTS (1'b0),
+      .USRDONEO  (1'b1),
+      .USRDONETS (1'b0));
+
    bscan_tap tap
      (.clk            (clk_core),
       .rst            (rst_core),
@@ -182,10 +203,10 @@ module swervolf_nexys_a7
       .dmi_reg_en     (dmi_reg_en   ),
       .dmi_reg_wr_en  (dmi_reg_wr_en),
       .dmi_hard_reset (dmi_hard_reset),
-      .o_flash_sclk   (),
-      .o_flash_cs_n   (),
-      .o_flash_mosi   (),
-      .i_flash_miso   (1'b0),
+      .o_flash_sclk   (flash_sclk),
+      .o_flash_cs_n   (o_flash_cs_n),
+      .o_flash_mosi   (o_flash_mosi),
+      .i_flash_miso   (i_flash_miso),
       .i_uart_rx      (i_uart_rx),
       .o_uart_tx      (cpu_tx),
       .o_ram_awid     (cpu.aw_id),